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Method of computing multi-conductor parasitic capacitances for VLSI circuits

  • US 5,452,224 A
  • Filed: 08/07/1992
  • Issued: 09/19/1995
  • Est. Priority Date: 08/07/1992
  • Status: Expired due to Fees
First Claim
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1. A method of designing and fabricating an electrical circuit, comprising the steps of:

  • producing a tentative electrical circuit design having a physical layout,computing parasitic capacitances between multiple electrical conductors within said electrical circuit design by;

    computing a division of the physical layout of said electrical circuit design into a plurality of windows in which at least one of said windows overlays at least one other of said windows, with at least some of said windows including respective pluralities of electrical conductors and at least one of said overlaps including at least one pair of electrical conductors,for each window, determining the parasitic capacitance values associated with the electrical conductors of that window by the method of partial capacitances, andcombining the parasitic capacitance values of said windows, and averaging the parasitic capacitance values of electrical conductor pairs included in a window overlap between the windows forming said overlap, to obtain a set of parasitic capacitances for said electrical circuit,adjusting said tentative circuit design to correct for any excessive computed parasitic capacitances, andfabricating electrical circuits in accordance with said adjusted circuit design.

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