Method of computing multi-conductor parasitic capacitances for VLSI circuits
First Claim
1. A method of designing and fabricating an electrical circuit, comprising the steps of:
- producing a tentative electrical circuit design having a physical layout,computing parasitic capacitances between multiple electrical conductors within said electrical circuit design by;
computing a division of the physical layout of said electrical circuit design into a plurality of windows in which at least one of said windows overlays at least one other of said windows, with at least some of said windows including respective pluralities of electrical conductors and at least one of said overlaps including at least one pair of electrical conductors,for each window, determining the parasitic capacitance values associated with the electrical conductors of that window by the method of partial capacitances, andcombining the parasitic capacitance values of said windows, and averaging the parasitic capacitance values of electrical conductor pairs included in a window overlap between the windows forming said overlap, to obtain a set of parasitic capacitances for said electrical circuit,adjusting said tentative circuit design to correct for any excessive computed parasitic capacitances, andfabricating electrical circuits in accordance with said adjusted circuit design.
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Accused Products
Abstract
A method of computing parasitic capacitances between multiple electrical conductors within an electric circuit computes a division of the circuit'"'"'s physical layout into a plurality of windows. The parasitic capacitances associated with the conductors of each window are computed, and the results for the various windows combined into a matrix of parasitic capacitances for the overall circuit. The windows are preferably overlapped, with the capacitance values for conductor pairs located in more than one window averaged. Complex polygons are fractured into simpler shapes by extending a ray from a vertex of the polygon to intersect an opposed segment, and defining the peripheries of the simpler elements as comprising the ray and respective different portions of the original polygon'"'"'s periphery. Rays may be extended in a x,y pattern from multiple vertices of the polygon until a ray is located that extends through the polygon'"'"'s interior, with the fracturing performed along that ray. Fracturing preferably continues until all of the elements are reduced to Manhattan-oriented rectangles or triangles. Where one element overlaps another element in another plane, fracturing is performed along a projection of the overlapping edge on the second element to reduce inaccuracies in the approximated charge density on the overlapped element.
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Citations
29 Claims
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1. A method of designing and fabricating an electrical circuit, comprising the steps of:
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producing a tentative electrical circuit design having a physical layout, computing parasitic capacitances between multiple electrical conductors within said electrical circuit design by; computing a division of the physical layout of said electrical circuit design into a plurality of windows in which at least one of said windows overlays at least one other of said windows, with at least some of said windows including respective pluralities of electrical conductors and at least one of said overlaps including at least one pair of electrical conductors, for each window, determining the parasitic capacitance values associated with the electrical conductors of that window by the method of partial capacitances, and combining the parasitic capacitance values of said windows, and averaging the parasitic capacitance values of electrical conductor pairs included in a window overlap between the windows forming said overlap, to obtain a set of parasitic capacitances for said electrical circuit, adjusting said tentative circuit design to correct for any excessive computed parasitic capacitances, and fabricating electrical circuits in accordance with said adjusted circuit design. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of computing the division of an electrically conductive, multi-vertex polygon in an electrical circuit into a plurality of simpler geometric elements in order to facilitate the computation of parasitic capacitances within said electrical circuit by the method of partial capacitances, comprising:
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establishing a mutually orthogonal x-y coordinate system extending a ray from a vertex of said polygon through the polygon in an x or y direction to intersect an opposed segment of the polygon, and thereby establish subpolygons of said poly on that are bounded in part by said ray, determining whether said subpolygons are all either triangles or Manhattan-oriented rectangles based upon said coordinate system, if said determination is positive, defining the peripheries of said simpler geometric elements as comprising said subpolygons, and if said determination is negative, extending at least one additional ray from at least one vertex of said polygon through respective subpolygons in an x or y direction to intersect respective opposed segments of the polygon and thereby establish additional subpolygons, bounded in part by their respective additional rays, until said polygon is divided into a set of subpolygons that are all either triangles or Manhattan-oriented rectangles based upon said x-y coordinate system. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A method of designing and fabricating an electrical circuit, comprising the steps of:
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producing a tentative electrical circuit design having a physical layout with a plurality of electrically conductive polygons in respective planes, computing the parasitic capacitance between a first electrically conductive polygon in a first plane and a second electrically conductive polygon in a second plane that is generally parallel to but spaced from the first plane, in which an edge of the first polygon is aligned with the interior of the second polygon, by; dividing said second conductive polygon into a plurality of geometric elements, with at least some of said geometric elements having a common edge that is aligned with said first conductive polygon edge, and none of the interiors of said geometric elements overlapping said first conductive polygon edge, and determining separately for each of the geometric elements of said second conductive polygon, by the method of partial capacitances, the parasitic capacitance associated with said first conductive polygon and the geometric elements of said second conductive polygon, adjusting said tentative circuit design to correct for any excessive computed parasitic capacitances, and fabricating electrical circuits in accordance with said adjusted circuit design. - View Dependent Claims (24)
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25. A computer programmed to compute parasitic capacitances between multiple electrical conductors within an electrical circuit that has a known physical layout, said computer comprising:
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means for computing a division of the physical layout of said electrical circuit into a plurality of windows in which at least one of said windows overlays at least one other of said windows, with at least some of said windows including respective pluralities of electrical conductors and at least one of said overlaps including at least one pair of electrical conductors, means for determining for each window, the parasitic capacitance values associated with the electrical conductors of that window by the method of partial capacitances, and means for combining the parasitic capacitance values of said windows, and averaging the parasitic capacitance values of electrical conductor pairs included in a window overlap between the windows forming said overlap, to obtain a set of parasitic capacitances for said electrical circuit.
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26. A computer programmed to compute the parasitic capacitance between a first electrically conductive polygon in a first plane and a second electrically conductive polygon in a second plane that is generally parallel to but spaced from the first plane, in which an edge of the first polygon is aligned with the interior of the second polygon, said computer comprising:
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means for dividing said second conductive polygon into a plurality of geometric elements, with at least some of said geometric elements having a common edge that is aligned with said first conductive polygon edge, and none of the interiors of said geometric elements overlapping said first conductive polygon edge, and means for determining separately for each of the geometric elements of said second conductive polygon, by the method of partial capacitances, the parasitic capacitance associated with said first conductive polygon and the geometric elements of said second conductive polygon.
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27. A machine having a memory which contains data representing a set of parasitic capacitances between multiple electrical conductors within an electrical circuit that has a known physical layout, said data generated by the method of:
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computing a division of the physical layout of said electrical circuit into a plurality of windows in which at least one of said windows overlays at least one other of said windows, with at least some of said windows including respective pluralities of electrical conductors and at least one of said overlaps including at least one pair of electrical conductors, determining, for each window, the parasitic capacitance values associated with the electrical conductors of that window by the method of partial capacitances, and combining the parasitic capacitance values of said windows, and averaging the parasitic capacitance values of electrical conductor pairs included in a window overlap between the windows forming said overlap.
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28. A machine having a memory which contains data representing a set of parasitic capacitance between a first electrically conductive polygon in a first plane and a second electrically conductive polygon in a second plane that is generally parallel to but spaced from the first plane, in which an edge of the first polygon is aligned with the interior of the second polygon, said data generated by the method of:
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dividing said second conductive polygon into a plurality of geometric elements, with at least some of said geometric elements having a common edge that is aligned with said first conductive polygon edge, and none of the interiors of said geometric elements overlapping said first conductive polygon edge, and determining separately for each of the geometric elements of said second conductive polygon, by the method of partial capacitances, the parasitic capacitance associated with said first conductive polygon and the geometric elements of said second conductive polygon.
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29. A method of computing the division of electrically conductive, multi-vertex polygons in an electrical circuit into respective pluralities of simpler geometric elements in order to facilitate the computation of parasitic capacitances within said electrical circuit by the method of partial capacitances, for use with electrically conductive polygons in generally parallel but mutually spaced planes in which an edge of a first conductive polygon in one plane is aligned with the interior of a second conductive polygon in the other plane, comprising:
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dividing said first conductive polygon into simpler geometric elements, and dividing said second conductive polygon into geometric elements of which at least some have a common edge that lies along a projection of said first conductive polygon edge onto the second conductive polygon, with none of the interiors of said second polygon'"'"'s geometric elements traversed by said projected edge of the first conductive polygon.
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Specification