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Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system

  • US 5,452,239 A
  • Filed: 02/26/1993
  • Issued: 09/19/1995
  • Est. Priority Date: 01/29/1993
  • Status: Expired due to Term
First Claim
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1. In a hardware emulation system, a method of removing gated clocks from clock nets in a circuit design comprising the steps of:

  • (a) identifying the clock nets in the netlist;

    (b) identifying clock sources, said clock sources being unique clock signals in the clock nets;

    (c) identifying sites where logic in the clock net is connected to a clock pin on a flip-flop;

    (d) determining whether pre-existing logic is connected to a clock enable pin on said flip-flop;

    (e) determining whether said logic in the clock net is clock-gating logic or clock generation logic;

    (f) transforming said logic in the clock net into functional equivalent logic if said clock net logic is clock-gating logic;

    (g) connecting said functional equivalent logic to said clock enable pin on said flip-flop if there is no pre-existing logic connected to said clock enable pin;

    (h) creating an AND gate having an output and a first input and a second input and connecting said output of said AND gate to said clock enable pin of said flip-flop, connecting said functional equivalent logic to said first input on said AND gate and transferring said pre-existing logic to said second input on said AND gate, if pre-existing logic is connected to said clock enable;

    (i) connecting said clock sources to said clock pin on said flip-flop, thereby creating a modified netlist; and

    (j) mapping said modified netlist into said hardware emulation system.

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