Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system

• US 5,452,239 A
• Filed: 02/26/1993
• Issued: 09/19/1995
• Est. Priority Date: 01/29/1993
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Varghese, Joseph, Galbiati, Louis III, Bui, Dam V., Sample, Stephen P., Dai, Wei-Jin
• Primary Examiner(s): Ramirez, Ellis B.
• Assistant Examiner(s): MILLER, CRAIG S
• Application Number:
  US08/000,844
• Time in Patent Office: 935 Days
• Field of Search: 364/578-580, 364/232.3, 364/927.81, 371/16.2, 371/22.1, 371/22.2, 371/23, 371/27, 340/825.22, 340/825.06, 340/825.88, 340/825.89, 340/825.83, 340/825.84, 307/465, 307/468, 307/219, 307/303, 357/45, 395/500, 365/201, 370/13, 370/14, 370/17
• US Class Current: 703/19
• CPC Class Codes: G06F 2117/04 Clock gating
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.

Claims

1. In a hardware emulation system, a method of removing gated clocks from clock nets in a circuit design comprising the steps of:

(a) identifying the clock nets in the netlist;

(b) identifying clock sources, said clock sources being unique clock signals in the clock nets;

(c) identifying sites where logic in the clock net is connected to a clock pin on a flip-flop;

(d) determining whether pre-existing logic is connected to a clock enable pin on said flip-flop;

(e) determining whether said logic in the clock net is clock-gating logic or clock generation logic;

(f) transforming said logic in the clock net into functional equivalent logic if said clock net logic is clock-gating logic;

(g) connecting said functional equivalent logic to said clock enable pin on said flip-flop if there is no pre-existing logic connected to said clock enable pin;

(h) creating an AND gate having an output and a first input and a second input and connecting said output of said AND gate to said clock enable pin of said flip-flop, connecting said functional equivalent logic to said first input on said AND gate and transferring said pre-existing logic to said second input on said AND gate, if pre-existing logic is connected to said clock enable;

(i) connecting said clock sources to said clock pin on said flip-flop, thereby creating a modified netlist; and

(j) mapping said modified netlist into said hardware emulation system.

2. The method of claim 1 further comprising the steps of:

(a) determining if any of said clock nets that were transformed have logic emanating from a branch point in said clock path leading to clock source and said branch leads to a data path;

(b) determining if any of said clock nets that could not be transformed have logic emanating from a branch point; and

(c) duplicating said logic in said clock path from said branch point to said source clock if either of the conditions to be determined in steps (a) or (b) exist.