Static semiconductor memory device adapted for stabilization of low-voltage operation and reduction in cell size

• US 5,452,246 A
• Filed: 01/28/1994
• Issued: 09/19/1995
• Est. Priority Date: 06/02/1993
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kawashima, Shoichiro
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/187,454
• Time in Patent Office: 599 Days
• Field of Search: 365/154, 365/149, 365/185, 365/208
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/418 Address circuits

Abstract

In a static type semiconductor memory device having a memory cell, the memory cell includes a flip-flop which has first and second nodes, a first transfer gate transistor which is connected between a first bit line of a pair of complementary bit lines and the first node, a second transfer gate transistor which is connected between a second bit line of the pair of complementary bit lines and the second node, a first capacitor which is connected between a word line and the gate of the first transfer gate, and a second capacitor which is connected between the word line and the gate of the second transfer gate. By the structure, even if the cell ratio is made small, it is possible to achieve stable operation at a low operating voltage and possible, thereby, to achieve both low power consumption and a high degree of integration.

Claims

1. A static type semiconductor memory device including a memory cell comprising:

a flip-flop having first and second nodes;

a first transfer gate transistor connected between a first bit line of a complementary pair of bit lines and a said first node;

a second transfer gate transistor connected between the second bit line of said complementary pair of bit lines and said second node;

a first capacitor connected between a word line and the gate of said first transfer gate; and

a second capacitor connected between said word line and the gate of said second transfer gate.

2. A static type semiconductor memory device according to claim 1, further comprising a first resistance means connected between the gate of said first transfer gate transistor and said first node, and a second resistance means connected between the gate of said second transfer gate transistor and said second node.

3. A static type semiconductor memory device according to claim 2, further comprising a word line drive circuit, said word line drive circuit applying to a non-selected word line in the write mode a low voltage which is lower than a low-potential power supply voltage of said flip-flop.

4. A static type semiconductor memory device according to claim 3, wherein said word line drive circuit applies to a selected word line in the write mode a high voltage which is higher than a high-potential power supply voltage of said flip-flop.

5. A static type semiconductor memory device according to claim 1, wherein said first capacitor is formed by providing a first insulation layer between said word line and the gate of said first transfer gate, and wherein said second capacitor is formed by providing a second insulation layer between said word line and the gate of said second transfer gate.

6. A static type semiconductor memory device according to claim 1, further comprising a third capacitor connected between said first bit line and the gate of said first transfer gate, and a fourth capacitor connected between said second bit line and the gate of said second transfer gate.

7. A static type semiconductor memory device according to claim 1, wherein said first transfer gate transistor and said second transfer gate transistor are each formed by a transistor having a double-gate structure.

8. A static type semiconductor memory device including a memory cell comprising:

a first load element and a second load element, one end of each of which is connected to a first power supply line that supplies a high-potential power supply voltage;

a first transistor, the drain of which is connected to the other end of said first load element, the source of which is connected to a second power supply line which supplies a low-potential power supply voltage, and the gate of which is connected to the other end said second load element;

a second transistor, the drain of which is connected to the other end of said second load element, the source of which is connected to said second power supply line, and the gate of which is connected to the other end of said first load element;

a third transistor, the drain of which is connected to a first of a pair of complementary bit lines and the source of which is connected to the other end of said first load element;

a fourth transistor, the drain of which is connected to a second of said pair of complementary bit lines and the source of which is connected to the other end of said second load element;

a first capacitor, one end of which is connected to a word line and the other end of which is connected to the gate of said third transistor;

a second capacitor, one end of which is connected to said word line and the other end of which is connected to the gate of said fourth transistor;

a first resistance means, one end of which is connected to the gate of said third transistor and the other end of which is connected to the other end of said first load element;

a second resistance means, one end of which is connected to the gate of said fourth transistor and the other end of which is connected to the other end of said second load element;

a third capacitor, one end of which is connected to said first bit line and the other end of which is connected to the gate of said third transistor; and

a fourth capacitor, one end of which is connected to said second bit line and the other end of which is connected to the gate of said fourth transistor.

9. A static type semiconductor memory device according to claim 8, comprising a word line drive circuit which controls the voltage level on the word line depending upon whether said memory cell is selected or non-selected, said word line drive circuit, in the case in which said memory cell is selected when writing, applying to the corresponding word line a high voltage which is higher than said high-potential power supply voltage.

10. A static type semiconductor memory device according to claim 8, wherein said first capacitor is formed by providing a first insulation layer between said word line and the gate of said third transistor, and wherein said second capacitor is formed by providing a second insulation layer between said word line and the gate of said forth transistor.

11. A static type semiconductor memory device according to claim 8, wherein said third capacitor is formed by providing a first insulation layer between a first conductive layer connected to said first bit line and the gate of said third transistor, and wherein said fourth capacitor is formed by a providing a second insulation layer between a second conductive layer connected to said second bit line and the gate of said fourth transistor.

12. A static type semiconductor memory device according to claim 8, wherein said third and fourth transistors are each formed by a transistor having a double-gate structure.