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Method and apparatus to improve read reliability in semiconductor memories

  • US 5,452,311 A
  • Filed: 10/30/1992
  • Issued: 09/19/1995
  • Est. Priority Date: 10/30/1992
  • Status: Expired due to Term
First Claim
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1. A method for controlling a period during which the output circuitry of a memory array waits before latching the output data comprising the steps of:

  • selecting an address to be read from the memory array,providing a signal to initiate a read operation at the selected address,latching output data provided by the read operation at the selected address after a first predetermined period,interrogating the data latched to detect the presence of an error in the data read from the memory array,continuing the operation of reading data at any next address following the selected address if the presence of an error is not detected, andrepeating the operation of reading data at the selected address if the presence of an error is detected with output data being latched after a second longer predetermined period.

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