Method and apparatus to improve read reliability in semiconductor memories

• US 5,452,311 A
• Filed: 10/30/1992
• Issued: 09/19/1995
• Est. Priority Date: 10/30/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven, Mielke, Neal
• Primary Examiner(s): CANNEY, VINCENT P
• Application Number:
  US07/969,756
• Time in Patent Office: 1,054 Days
• Field of Search: 371/5.1, 371/5.5, 371/21.1, 371/21.4, 371/28, 371/51.1, 371/, 395/575
• US Class Current: 714/805
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

Claims

1. A method for controlling a period during which the output circuitry of a memory array waits before latching the output data comprising the steps of:

selecting an address to be read from the memory array,

providing a signal to initiate a read operation at the selected address,

latching output data provided by the read operation at the selected address after a first predetermined period,

interrogating the data latched to detect the presence of an error in the data read from the memory array,

continuing the operation of reading data at any next address following the selected address if the presence of an error is not detected, and

repeating the operation of reading data at the selected address if the presence of an error is detected with output data being latched after a second longer predetermined period.

2. A method for controlling a period during which the output circuitry of a memory array waits before latching the output data as claimed in claim 1 comprising the steps of;

continuing to repeat the operation of reading data at the selected address for a selected number of times with an output signal being latched after a continually longer predetermined periods as long as the presence of an error is detected.

3. A method for controlling a period during which the output circuitry of a memory array waits before latching the output data comprising the steps of;

interrogating a selected address of a memory array to read data thereat,

latching data read from the selected address after a first preselected period,

examining the data latched using error detecting means to determine whether an error has occurred in the data read,

utilizing the data read if no error has occurred, and repeating the process of interrogation of the selected address to read data thereat if an error has occurred in the data read while latching data read from the selected address after a period longer than the first preselected period.

4. A method for controlling a period during which the output circuitry of a memory array waits before latching the output data as claimed in claim 3 further comprising the step of attempting to correct any error detected after a repeating an attempt to read data at the selected address and determining that an error has occurred in the repeated attempt.

5. Apparatus for reading data from a memory array comprising:

means for selecting an address to be read from the memory array,

means for providing a signal to initiate a read operation at the selected address,

means for latching output data provided by the read operation at the selected address after a first predetermined period,

means for interrogating the data latched to detect the presence of an error in the data read from the memory array,

means for continuing the operation of reading data at any next address following the selected address if the presence of an error is not detected, and

means for repeating the operation of reading data at the selected address if the presence of an error is detected with output data being latched after a second longer predetermined period.

6. Apparatus for reading data from a memory array as claimed in claim 5 in which the means for selecting an address to be read from the memory array comprises means for selecting a plurality of sequential addresses included in a sector of a memory array, and

in which the means for interrogating the data latched to detect the presence of an error in the data read from the memory array operates on the data read from an entire sector of the memory array.

7. Apparatus for reading data from a memory array as claimed in claim 6 in which the means for selecting a plurality of sequential addresses included in a sector of a memory array comprises means for storing an address, means for storing a count of addresses to be read, means for incrementing an address stored by the means for storing an address, and means for decrementing a count stored by the means for storing a count of addresses to be read.

8. Apparatus for reading data from a memory array as claimed in claim 5 further comprising means for continuing to repeat the operation of reading data at the selected address a selected number of times with an output signal being latched after continually longer predetermined periods as long as the presence of an error is detected.

9. Apparatus for reading data from a memory array comprising:

circuitry for selecting an address to be read from the memory array;

circuitry for providing a signal to initiate a read operation at the selected address;

a data latch which latches output data provided by the read operation at the selected address after a first predetermined period;

error detection circuitry for interrogating the data latched to detect the presence of an error in the data read from the memory array;

circuitry for continuing the operation of reading data at any next address following the selected address if the presence of an error is not detected; and

circuitry for repeating the operation of reading data at the selected address if the presence of an error is detected with output data being latched after a second longer predetermined period.

10. Apparatus for reading data from a memory array as claimed in claim 9 in which the circuitry for selecting an address to be read from the memory array comprises circuitry for selecting a plurality of sequential addresses included in a sector of a memory array, and in which the error detection circuitry operates on the data read from an entire sector of the memory array.

11. Apparatus for reading data from a memory array as claimed in claim 10 in which the circuitry for selecting a plurality of sequential addresses included in a sector of a memory array comprises an address register for storing an address, a count register for storing a count of addresses to be read, an incrementer circuit for incrementing an address stored by the address register, and a decrementer circuit for decrementing a count stored by the count register.

12. Apparatus for reading data from a memory array as claimed in claim 9 further comprising circuitry for continuing to repeat the operation of reading data at the selected address a selected number of times with an output signal being latched after continually longer predetermined periods as long as the presence of an error is detected.