Anisotropic polysilicon plasma etch using fluorine gases
First Claim
1. The process of etching a polysilicon gate on a suitable substrate through a patterned resist layer which will not undercut the polysilicon layer which process comprises:
- etching said polysilicon layer with a first flow of helium and fluorine containing gases into a plasma reactive etching chamber containing said semiconductor substrate;
etching said polysilicon layer with a second flow of helium and chlorine gases into the plasma reactive etching chamber containing said semiconductor substrate;
detecting the endpoint of the completion of etching of the polysilicon layer and stopping the flow of said chlorine gas;
etching said polysilicon layer with a third flow of mixture of fluorine containing gas and helium gases into the plasma reactive etching chamber containing said semiconductor substrate; and
etching said polysilicon layer with a fourth flow of helium and chlorine gases into the plasma reactive etching chamber containing said semiconductor substrate to thereby etch and pattern portions of the polysilicon layer forming the polysilicon gate.
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Accused Products
Abstract
A process for dry etching a polysilicon layer or gate structure of an integrated circuit is achieved. More particularly, a process for overetching a polysilicon layer using, in place of a conventional chloride gas (e.g., CCl4), a fluorine gas, such as C2 F6 or CF4 is disclosed. After the main etch step, a passivation formation step is performed where a mixture of helium and fluorine gases is flowed into a plasma etch chamber. Next, an overetch is performed by flowing a mixture of helium and chlorine gas. This process eliminates the need to use CCl4 or other harmful ozone containing gases in the overetch step. Moreover, an acceptable polysilicon sidewall profile is achieved and no undercutting of the polysilicon layer is experienced using this process.
34 Citations
24 Claims
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1. The process of etching a polysilicon gate on a suitable substrate through a patterned resist layer which will not undercut the polysilicon layer which process comprises:
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etching said polysilicon layer with a first flow of helium and fluorine containing gases into a plasma reactive etching chamber containing said semiconductor substrate; etching said polysilicon layer with a second flow of helium and chlorine gases into the plasma reactive etching chamber containing said semiconductor substrate; detecting the endpoint of the completion of etching of the polysilicon layer and stopping the flow of said chlorine gas; etching said polysilicon layer with a third flow of mixture of fluorine containing gas and helium gases into the plasma reactive etching chamber containing said semiconductor substrate; and etching said polysilicon layer with a fourth flow of helium and chlorine gases into the plasma reactive etching chamber containing said semiconductor substrate to thereby etch and pattern portions of the polysilicon layer forming the polysilicon gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. The process of etching a polysilicon gate from a polysilicon layer on a suitable substrate through a patterned resist layer that exposes portions of the polysilicon layer in a plasma reactive etch chamber which minimizes undercutting of the polysilicon layer, which process comprises:
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etching said polysilicon layer so to remove the majority of the exposed polysilicon layer; etching said polysilicon layer with a passivation formation etch step with the use of an etch gas comprising a mixture of fluorine containing gas and helium gases in the plasma reactive etching chamber containing said semiconductor wafer; and etching said polysilicon layer with an overetch step with the use of an etch gas comprising helium and chlorine gases in the plasma reactive etching chamber containing said semiconductor wafer. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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Specification