Method for making an interconnection structure for integrated circuits

• US 5,453,404 A
• Filed: 03/24/1994
• Issued: 09/26/1995
• Est. Priority Date: 10/13/1992
• Status: Expired due to Term

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn Leedy
• Inventors: Leedy, Glenn
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US08/217,410
• Time in Patent Office: 551 Days
• Field of Search: 437/203, 437/225, 437/204, 437/211, 437/180, 437/206, 437/209, 148/DIG. 20, 156/643, 156/645
• US Class Current: 438/479
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01045 Rhodium [Rh]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10S 438/97 : Specified etch stop material

Abstract

A device for making temporary or permanent electrical connections to circuit pads of an integrated circuit is made with conventional semiconductor fabrication processes. The device has a supporting substrate from which project a plurality of insertion structures that are in mating alignment with corresponding circuit pads of the integrated circuit. Each insertion structure is metallized to make electrical contact with the corresponding circuit pad. The electrical contacts may be temporary or permanent depending upon the choice of metallization and the pressure applied to the contacting surfaces. The insertion structure devices have particular application for functional testing, electrical burn-in and packaging of an integrated circuit either as a full wafer or as an individual die.

Claims

1. A method of fabricating a device for making electrical contact with an integrated circuit comprising the steps of:

(a) depositing a mask layer on a surface of a sacrificial substrate;

(b) etching a pattern of apertures through the mask layer;

(c) etching the sacrificial substrate exposed by the pattern of apertures to form a pattern of wells with tapering side walls;

(d) depositing a layer of conductive material within each of the wells;

(e) depositing a layer of dielectric material over the structure formed in step (d);

(f) etch removing the sacrificial substrate to expose at least a tip portion of the conductive material deposited within each of the wells, thereby forming a pattern of projecting insertion structures.

2. The method of claim 1 wherein the sacrificial substrate is silicon.

3. The method of claim 2 wherein the silicon has a <

100>

crystal orientation.

4. The method of claim 1 wherein the dielectric material is selected from the group consisting of silicon dioxide and silicon nitride.

5. The method of claim 4 wherein the dielectric material has a tensile stress of approximately 1×

10⁸ dynes/cm².

6. The method of claim 5 wherein the dielectric material is deposited to form the mask layer.

7. The method of claim 1 wherein the sacrificial substrate is entirely removed in step (f).

8. The method of claim 1 further comprising the step of forming an etch stop layer on the sacrificial substrate followed by the step of forming a semiconductor layer over the etch stop layer and then removing the sacrificial substrate in step (f) to the etch stop layer.

9. The method of claim 8 further comprising the step of removing the etch stop layer.

10. The method of claim 9 further comprising the step of fabricating an integrated circuit on said semiconductor layer.

11. The method of claim 8 wherein the etch stop layer is an epitaxial layer.

12. The method of claim 11 wherein the etch stop layer is germanium boron doped silicon.

13. The method of claim 12 wherein the etch stop layer has a dopant concentration of approximately 2×

10²⁰ boron atoms/cm³.

14. The method of claim 11 wherein the semiconductor layer is an epitaxial layer.

15. The method of claim 14 wherein the dielectric material is selected from the group consisting of silicon nitride and silicon dioxide.

16. The method of claim 15 wherein the dielectric material has a tensile stress of approximately 1×

10⁸ dynes/cm².

17. The method of clam 16 wherein the dielectric material is deposited to form the mask layer.

18. A method of fabricating an integrated circuit with integral insertion structures comprising the steps of:

(a) forming an etch stop layer on a semiconductor substrate;

(b) forming a circuit grade semiconductor layer over the etch stop layer;

(c) depositing a mask layer on an exposed surface of the circuit grade semiconductor layer;

(d) etching a pattern of apertures through the mask layer;

(e) etching a pattern of wells with tapering side walls into the semiconductor substrate underlying the pattern of apertures;

(f) depositing a layer of conductive material within each of the wells;

(g) depositing a layer of dielectric material over the structure formed in step (f);

(h) etch removing the semiconductor substrate to the etch stop layer to expose at least a tip portion of the conductive material deposited within each of the wells, thereby forming a pattern of projecting insertion structures;

(i) removing the etch stop layer to expose the circuit grade semiconductor layer.

19. The method of claim 18 wherein the semiconductor substrate is silicon.

20. The method of claim 19 wherein the silicon has a <

100>

crystal orientation.

21. The method of claim 18 wherein the etch stop layer is an epitaxial layer.

22. The method of claim 21 wherein the etch stop layer is germanium-boron doped silicon.

23. The method of claim 22 wherein the etch stop layer has a dopant concentration of approximately 2×

10²⁰ boron atoms/cm³.

24. The method of claim 18 wherein the circuit grade semiconductor layer is an epitaxial layer.

25. The method of claim 24 further comprising the step of fabricating an integrated circuit on said circuit grade semiconductor layer.