Planarized semiconductor structure using subminimum features

• US 5,453,639 A
• Filed: 10/27/1993
• Issued: 09/26/1995
• Est. Priority Date: 09/04/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Landis, Howard S., Cronin, John E.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): BROWN, PETER T
• Application Number:
  US08/144,162
• Time in Patent Office: 699 Days
• Field of Search: 257/506, 257/510-521, 437/62
• US Class Current: 257/510
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: Y10S 438/945 Special, e.g. metal

Abstract

Improved, planarized semiconductor structures are described. They are prepared by a method which involves the creation of a series of subminimum (i.e., 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.

Claims

1. A planarized semiconductor structure comprising:

a semiconductor structure having a recessed area therein and having a surface adjacent said recessed area;

a plurality of dispersed, oxidized pillars situated within said recessed area; and

a planarized layer of fill comprising a chemical vapor-deposited oxide material, said layer of fill deposited over said pillars and said recessed area, wherein a second surface of said planarized layer of fill is substantially planar with said surface of said semiconductor structure, and wherein the oxidized pillars have a crystal structure which is different from that of the planarized layer of fill.

2. The planarized semiconductor structure of claim 1 wherein said pillars comprise a thermal oxide and said fill comprises a chemical vapor deposited oxide.

3. The planarized semiconductor structure of claim 1 wherein the density of said pillars comprises one to ten pillars per square micron.

4. The planarized semiconductor structure of claim 1 wherein said pillars further comprise a layer of oxide thereon.

5. The planarized semiconductor structure of claim 1 wherein said recessed area comprises a trench.