Binary FM demodulator with self-adjusting resonant operating frequency according to demodulated binary output signal duty cycle

• US 5,453,714 A
• Filed: 02/28/1995
• Issued: 09/26/1995
• Est. Priority Date: 03/10/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Madsen, Benny
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/396,441
• Time in Patent Office: 210 Days
• Field of Search: 329/300, 329/301, 329/302, 329/303, 329/337, 329/319, 329/325, 329/334, 329/336, 329/338, 329/339, 329/323, 375/80, 375/81, 375/82, 375/88, 375/89, 375/90, 375/91, 375/51, 375/99, 375/45, 375/60, 375/62
• US Class Current: 329/301
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 5/18 with frequency-determining element comprising distributed inductance and capacitance
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/152 using controlled oscillators, e.g. PLL arrangements
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/1492 with time compression, e.g. operating according to the ping-pong technique

Abstract

A demodulator for demodulating a binary frequency-modulated signal includes a demodulator with a quadrature tank circuit and a duty cycle monitor circuit. The quadrature tank circuit has a voltage-controllable resonant frequency for compensating for shifts in the carrier frequency of the incoming signal and shifts in the tank circuit component values so as to allow the use of a high-Q tank circuit and thereby maximize use of the incoming signal energy. The quadrature tank circuit is a reactive circuit (with both inductive and capacitive elements) which includes a varactor diode having a voltage-controllable capacitance. The duty cycle monitor circuit measures the duty cycle of the demodulated binary output from the demodulator, and provides a control voltage to the quadrature tank circuit for adjusting its center frequency of operation.

Claims

1. A demodulator with a selectable resonant frequency of operation for demodulating a frequency-modulated signal comprising:

demodulator means with an adjustable resonant frequency of operation for receiving and demodulating a frequency-modulated signal which has a signal carrier frequency associated therewith to produce a binary demodulated signal which has a duty cycle associated therewith, and for receiving a frequency control signal and in accordance therewith adjusting said adjustable resonant frequency of operation; and

controller means, coupled to said demodulator means for receiving and analyzing said binary demodulated signal duty cycle and in accordance therewith providing said frequency control signal.

2. A demodulator as recited in claim 1, wherein said demodulator means comprises a mixer and coupled thereto a phase delay circuit with said adjustable resonant frequency of operation associated therewith, wherein said mixer and phase delay circuit receive said frequency-modulated signal, said phase delay circuit provides a phase-delayed frequency-modulated signal to said mixer, and said mixer mixes said frequency-modulated and phase-delayed frequency-modulated signals to provide said binary demodulated signal, and further wherein said phase delay circuit includes adjuster means for receiving said frequency control signal and in accordance therewith adjusting said adjustable resonant frequency of operation.

3. A demodulator as recited in claim 2, wherein said phase delay circuit comprises a quadrature tank circuit.

4. A demodulator as recited in claim 2, wherein said adjuster means comprises a varactor diode.

5. A demodulator as recited in claim 1, wherein said controller means comprises a duty cycle monitor for measuring said binary demodulated signal duty cycle and in accordance therewith providing said frequency control signal.

6. A demodulator as recited in claim 5, wherein said duty cycle monitor comprises an integrator for integrating said binary demodulated signal to produce a dc output signal and in accordance therewith provide said frequency control signal.

7. A demodulator as recited in claim 1, wherein said controller means comprises comparator means for receiving and comparing said binary demodulated signal with a binary reference signal, and in accordance therewith providing said frequency control signal.

8. A demodulator as recited in claim 7, wherein said comparator means comprises:

sampler means for sampling said binary demodulated signal to provide a binary sample signal which represents a first plurality of logical ones and zeroes; and

binary comparator means, coupled to said sampler means, for receiving and comparing said binary sample signal with said binary reference signal which represents a second plurality of logical ones and zeroes, and in accordance therewith providing said frequency control signal.

9. A demodulator as recited in claim 7, wherein said comparator means comprises:

symbol timing recovery means for recovering from said binary demodulated signal a data signal which represents a plurality of serial binary data bits and a data clock signal associated therewith;

sampler means, coupled to said symbol timing recovery means for receiving and sampling said data signal to provide a data sample signal which represents a first plurality of logical ones and zeroes; and

binary comparator means, coupled to said sampler means, for receiving and comparing said data sample signal with said binary reference signal which represents a second plurality of logical ones and zeroes, and in accordance therewith providing said frequency control signal.

10. A demodulator as recited in claim 9, wherein said symbol timing recovery means comprises a phase-lock-loop.

11. A demodulator as recited in claim 9, wherein said symbol timing recovery means comprises a correlator.

12. A demodulator with a selectable resonant frequency of operation for demodulating a frequency-modulated signal, comprising:

a demodulator with an adjustable resonant frequency of operation which receives and demodulates a frequency-modulated signal which has a signal carrier frequency associated therewith and produces a binary demodulated signal which has a duty cycle associated therewith, and which receives a frequency control signal and in accordance therewith adjusts said adjustable resonant frequency of operation; and

a signal controller, coupled to said demodulator which receives and analyzes said binary demodulated signal duty cycle and in accordance therewith provides said frequency control signal.

13. A demodulator as recited in claim 12, wherein said demodulator comprises a mixer and coupled thereto a phase delay circuit with said adjustable resonant frequency of operation associated therewith, wherein said mixer and phase delay circuit receive said frequency-modulated signal, said phase delay circuit provides a phase-delayed frequency-modulated signal to said mixer, and said mixer mixes said frequency-modulated and phase-delayed frequency-modulated signals to provide said binary demodulated signal, and further wherein said phase delay circuit includes a circuit component with an adjustable value which receives said frequency control signal and in accordance therewith adjusts said adjustable resonant frequency of operation.

14. A demodulator as recited in claim 13, wherein said phase delay circuit comprises a quadrature tank circuit.

15. A demodulator as recited in claim 13, wherein said circuit component comprises a varactor diode.

16. A demodulator as recited in claim 12, wherein said signal controller comprises a duty cycle monitor circuit which measures said binary demodulated signal duty cycle and in accordance therewith provides said frequency control signal.

17. A demodulator as recited in claim 16, wherein said duty cycle monitor circuit comprises an integrator circuit which integrates said binary demodulated signal and produces a dc output signal, and in accordance therewith provides said frequency control signal.

18. A demodulator as recited in claim 12, wherein said signal controller comprises a signal comparison circuit which receives and compares said binary demodulated signal with a binary reference signal, and in accordance therewith provides said frequency control signal.

19. A demodulator as recited in claim 18, wherein said signal comparison circuit comprises:

a sampling circuit which samples said binary demodulated signal and provides a binary sample signal which represents a first plurality of logical ones and zeroes; and

a binary comparison circuit, coupled to said sampling circuit, which receives and compares said binary sample signal with said binary reference signal which represents a second plurality of logical ones and zeroes, and in accordance therewith provides said frequency control signal.

20. A demodulator as recited in claim 18, wherein said signal comparison circuit comprises:

a symbol timing recovery circuit for recovering from said binary demodulated signal data signal which represents a plurality of serial binary data bits and a data clock signal associated therewith;

a sampling circuit, coupled to said symbol timing recovery circuit, which receives and samples said data signal and provides a data sample signal which represents a first plurality of logical ones and zeroes; and

a binary comparison circuit, coupled to said sampling circuit, which receives and compares said data sample signal with said binary reference signal which represents a second plurality of logical ones and zeroes, and in accordance therewith provides said frequency control signal.

21. A demodulator as recited in claim 20, wherein said symbol timing recovery circuit comprises a phase-lock-loop.

22. A demodulator as recited in claim 20, wherein said symbol timing recovery circuit comprises a correlator.

23. A demodulation method for using a selectable resonant frequency of operation to demodulate a frequency-modulated signal, comprising the steps of:

receiving and demodulating with an adjustable resonant frequency of operation a frequency-modulated signal which has a signal carrier frequency associated therewith to produce a binary demodulated signal which has a duty cycle associated therewith;

receiving a frequency control signal and in accordance therewith adjusting said adjustable resonant frequency of operation; and

analyzing said binary demodulated signal duty cycle and in accordance therewith providing said frequency control signal.

24. A demodulation method as recited in claim 23, wherein said step of receiving and demodulating with an adjustable resonant frequency of operation a frequency-modulated signal which has a signal carrier frequency associated therewith to produce a binary demodulated signal comprises the steps of:

phase-delaying said frequency-modulated signal in accordance with said adjustable resonant frequency of operation to provide a phase-delayed frequency-modulated signal; and

mixing said frequency-modulated signal and said phase-delayed frequency-modulated signal in a mixer to provide said binary demodulated signal.

25. A demodulation method as recited in claim 24, wherein said step of phase-delaying said frequency-modulated signal in accordance with said adjustable resonant frequency of operation to provide a phase-delayed frequency-modulated signal comprises the step of inputting said frequency-modulated signal to a quadrature tank circuit.

26. A demodulation method as recited in claim 24, wherein said step of receiving a frequency control signal and in accordance therewith adjusting said adjustable resonant frequency of operation comprises the step of receiving said frequency control signal with a varactor diode.

27. A demodulation method as recited in claim 23, wherein said step of analyzing said demodulated signal and in accordance therewith providing said frequency control signal comprises the step of measuring said binary demodulated signal duty cycle and in accordance therewith providing said frequency control signal.

28. A demodulation method as recited in claim 27, wherein said step of measuring said binary demodulated signal duty cycle and in accordance therewith providing said frequency control signal comprises the step of integrating said binary signal to produce a dc output signal and in accordance therewith provide said frequency control signal.

29. A demodulation method as recited in claim 23, wherein said step of analyzing said binary demodulated signal and in accordance therewith providing said frequency control signal comprises the step of receiving and comparing said binary demodulated signal with a binary reference signal and in accordance therewith providing said frequency control signal.

30. A demodulation method as recited in claim 29, wherein said step of receiving and comparing said binary demodulated signal with a binary reference signal and in accordance therewith providing said frequency control signal comprises the steps of:

sampling said binary demodulated signal to provide a binary sample signal which represents a first plurality of logical ones and zeroes; and

comparing said binary sample signal with said binary reference signal which represents a second plurality of logical ones and zeroes, and in accordance therewith providing said frequency control signal.

31. A demodulation method as recited in claim 29, wherein said step of receiving and comparing said binary demodulated signal with a binary reference signal and in accordance therewith providing said frequency control signal comprises the steps of:

recovering from said binary demodulated signal a data signal which represents a plurality of serial binary data bits and a data clock signal associated therewith;

sampling said data signal to provide a data sample signal which represents a first plurality of logical ones and zeroes; and

comparing said data sample signal with said binary reference signal which represents a second plurality of logical ones and zeroes, and in accordance therewith providing said frequency control signal.

32. A demodulation method as recited in claim 31, wherein said step of recovering from said binary demodulated signal a data signal which represents a plurality of serial binary data bits and a data clock signal associated therewith comprises the step of recovering said data signal and said data clock signal from said binary demodulated signal with a phase-lock-loop.

33. A demodulation method as recited in claim 31, wherein said step of recovering from said binary demodulated signal data signal which represents a plurality of serial binary data bits and a data clock signal associated therewith comprises the step of recovering said data signal and said data clock signal from said binary demodulated signal with a correlator.