Multistandard video signal decoder
First Claim
1. A data decoding device for selectively or simultaneously decoding data of plural formats super-imposed at predetermined positions in a vertical blanking period of a video signal, said device comprising:
- extract pulse generator means for detecting line number and an intraline position in the vertical blanking period from a vertical sync signal and a horizontal sync signal of a composite video signal, and generating a line signal extract pulse, a data signal extract pulse and a reference signal extract pulse;
binary circuit means for converting the video signal into a binary signal;
phase-locked loop means for producing a data extract clock signal in synchronism with a clock reference signal extracted from the video signal on the basis of the line signal extract pulse and the reference signal extract pulse;
memory means supplied with the data extract clock signal and the binary signal in response to the line signal extract pulse and the data signal extract pulse, and storing a data signal therein from the binary signal in accordance with the data extract clock signal; and
control means capable of designating a plurality of durations for generating the line signal extract pulse, the data signal extract pulse and the reference signal extract pulse in said extract pulse generator means, and further capable of designating a plurality of frequency division ratios in said phase-locked loop means.
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Accused Products
Abstract
A data decoding device capable of decoding plural kinds of data superimposed in a vertical blanking period of a video signal. The device comprises means for detecting the line number and the intraline position in the vertical blanking period from vertical and horizontal sync signals and generating a line signal extract pulse, a data signal extract pulse and a reference signal extract pulse; binary circuit means for converting the video signal into a binary signal; PLL means for producing a data extract clock signal in synchronism with a clock reference signal extracted on the basis of the line signal extract pulse and the reference signal extract pulse; memory means supplied with the data extract clock signal and the binary signal in response to the line signal extract pulse and the data signal extract pulse, and storing the data signal therein; and control means capable of designating a plurality of durations for generating the respective extract pulses and a plurality of frequency division ratios in the PLL means. In the device, the circuits are usable in common to achieve curtailment in the production cost.
51 Citations
9 Claims
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1. A data decoding device for selectively or simultaneously decoding data of plural formats super-imposed at predetermined positions in a vertical blanking period of a video signal, said device comprising:
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extract pulse generator means for detecting line number and an intraline position in the vertical blanking period from a vertical sync signal and a horizontal sync signal of a composite video signal, and generating a line signal extract pulse, a data signal extract pulse and a reference signal extract pulse; binary circuit means for converting the video signal into a binary signal; phase-locked loop means for producing a data extract clock signal in synchronism with a clock reference signal extracted from the video signal on the basis of the line signal extract pulse and the reference signal extract pulse; memory means supplied with the data extract clock signal and the binary signal in response to the line signal extract pulse and the data signal extract pulse, and storing a data signal therein from the binary signal in accordance with the data extract clock signal; and control means capable of designating a plurality of durations for generating the line signal extract pulse, the data signal extract pulse and the reference signal extract pulse in said extract pulse generator means, and further capable of designating a plurality of frequency division ratios in said phase-locked loop means. - View Dependent Claims (2)
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3. A data decoding apparatus for decoding a plurality of data each super-imposed in one of a plurality of formats in a vertical blanking period of a video signal, said apparatus comprising:
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extract pulse generator means for determining a line number and an intraline position in the vertical blanking period from a vertical sync signal and a horizontal sync signal of a composite video signal, and generating a line signal extract pulse, a data signal extract pulse and a reference signal extract pulse, said line signal extract pulse corresponding to a horizontal line of said video signal; binary circuit means for converting the video signal into a binary signal, said binary signal including a binary data signal; means for extracting a clock reference signal from said binary signal as a function of said line signal extract pulse and said reference signal extract pulse; variable-frequency phase-locked loop means, having an oscillation frequency, for producing a data extract clock signal in synchronism with said clock reference signal; memory means, coupled to said binary circuit means and responsive to said data extract clock signal and said line signal extract pulse, for storing said binary data signal; and control means, coupled to said extract pulse generator means and said variable-frequency phase-locked loop means, for controlling a respective parameter of each of said line signal extract pulse, said data signal extract pulse and said reference signal extract pulse, and for controlling said oscillation frequency of said variable-frequency phase-locked loop means. - View Dependent Claims (4, 5, 6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneeSony Corporation (Sony Group Corp.)
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Original AssigneeSony Corporation (Sony Group Corp.)
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InventorsEzaki, Tadashi
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Primary Examiner(s)Kostak, Victor R.
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Assistant Examiner(s)Flynn, Nathan J.
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Application NumberUS08/130,469Time in Patent Office725 DaysField of Search348/461, 348/465, 348/466, 348/467, 348/473, 348/476, 348/477, 348/478, 348/479US Class Current348/461CPC Class CodesH04N 7/035 Circuits for the digital no...H04N 7/0352 for regeneration of the clo...H04N 7/0355 for discrimination of the b...
