Cache memory support in an integrated memory system

• US 5,454,107 A
• Filed: 11/30/1993
• Issued: 09/26/1995
• Est. Priority Date: 11/30/1993
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Lehman, Judson A., Nakahara, Mike, Richardson, Nicholas J.
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): BANANKHAH, MAJID A
• Application Number:
  US08/159,186
• Time in Patent Office: 665 Days
• Field of Search: 395/162, 395/425, 395/128, 395/325, 395/650, 358/160
• US Class Current: 711/153
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.

Claims

1. For use in a computing machine including a CPU and a cache memory both connected to a CPU bus and including a first backing store storing digital data, apparatus comprising:

means for programmably allocating address locations within a first logical portion of said first backing store as display memory and address locations within a second logical portion of said first backing store as main memory;

means, connected to said CPU and to said means for programmably allocating, for allowing substantially independent accesses of said CPU to said first and second logical portions of said first backing store;

means, connected to said first backing store and operatively connected to said means for allowing substantially independent accesses, for accessing respective ones of said first and second portions of said backing store in accordance with a dynamically-determined priority; and

cache controller means, connected to said CPU bus and to said means for allowing substantially independent accesses, for caching in said cache memory data from said first backing store.

2. The apparatus of claim 1 wherein said CPU bus carries a first signal directed from cache controller to said CPU for causing said CPU to abort a current bus cycle.

3. The apparatus of claim 2 wherein a connection between said cache controller means and said means for allowing substantially independent accesses includes a second signal directed from said cache controller means to said means for allowing substantially independent accesses for causing the means for allowing substantially independent accesses to abort a current access cycle.

4. The apparatus of claim 3 wherein said connection between said cache controller means and said means for allowing substantially independent accesses includes a third signal directed from said means for allowing substantially independent accesses to said cache controller means for alerting the cache controller means prior to a time that data from said backing store is driven on said CPU bus by said means for allowing substantially independent accesses.

5. The apparatus of claim 1 further comprising a second backing store and memory controller means connected to said cache controller means and to said second backing store.

6. The apparatus of claim 5 wherein said means for allowing substantially independent accesses further comprises means, responsive to an address on an address portion of said CPU bus and to said first signal, for aborting a current accesses cycle when said address corresponds to an address within said first backing store, and for continuing a current accesses when said address does not correspond to an address within said first backing store.