Method of fabricating porous silicon carbide (SiC)

• US 5,454,915 A
• Filed: 09/01/1993
• Issued: 10/03/1995
• Est. Priority Date: 10/06/1992
• Status: Expired due to Term

• Current Assignee: Kulite Semiconductor Products Inc
• Original Assignee: Kulite Semiconductor Products Inc
• Inventors: Kurtz, Anthony D., Shor, Joseph S.
• Primary Examiner(s): Valentine, Donald R.
• Application Number:
  US08/115,983
• Time in Patent Office: 762 Days
• Field of Search: 204/129.55, 204/129.3, 204/129.75, 204/129.65, 205/123-124
• US Class Current: 438/694
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 33/0054 for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/34 containing only elements of Group IV of the Periodic Table
• CPC Class Codes: Y10S 438/96 Porous semiconductor

Abstract

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Claims

1. A method of fabricating porous SiC comprising the steps of:

placing a wafer of silicon carbide in a electrochemical cell;

electrochemically etching said wafer for a period sufficient to form pores on a exposed surface of said wafer; and

illuminating said exposed surface of said wafer with ultraviolet (UV) light.

2. The method according to claim 1, wherein said wafer is n-type SiC.

3. The method according to claim 2, wherein said n-type SiC has a carrier concentration of about 3×

10¹⁸ /cm³ with said SiC being 6H-SiC.

4. The method according to claim 1 wherein said wafer is p-type SiC.

5. The method according to claim 4, wherein said p-type SiC has a carrier concentration of between 2 to 3×

10¹⁸ /cm³.

6. The method according to claim 5, wherein said step of electrochemically etching includes applying an anodic potential of from 2 to 3 V at a saturated reference electrode for 1 to 60 minutes.

7. The method according to claim 1, wherein the intensity of said UV light is between 50-500 mW/cm³ and the wavelength is between 250-400 nanometers.

8. The method according to claim 1, wherein said step of electrochemically etching includes applying an anodic potential to said wafer in said cell.

9. The method according to claim 8, wherein said potential is between 0-3 volts.

10. The method according to claim 1, wherein said etching employs hydrofluoric acid (HF).

11. The method according to claim 10, wherein said HF is 2.5% in water.

12. The method according to claim 1, further including oxidizing porous portions of said wafer after said etching step to convert said porous silicon carbide into silicon dioxide.

13. The method according to claim 12, further including densifying the regions of silicon dioxide.

14. The method according to claim 13, wherein said densifying step comprises annealing said regions of silicon dioxide.

15. The method according to claim 1, wherein pores of submicron dimensions are formed during said etching step.

16. The method according to claim 1, wherein a monocrystalline layer of porous silicon carbide is formed during said etching step.

17. The method according to claim 1, wherein said pores spacings are less than 10 nm.

18. The method according to claim 1, further including the step of passivating a surface of said layer.

19. The method according to claim 18, wherein said passivating step comprises forming a thin insulating layer on the surface of the said porous layer.

24. The process to claim 2 for providing a heterojunction of porous SiC and non-porous SiC.

20. A process for etching silicon carbide comprising:

providing a substrate or epilayer of silicon carbide, said silicon carbide being of a first conductivity type;

selectively anodizing said substrate electrochemically to form porous regions of silicon carbide thereon; and

removing said porous regions from said substrate.

21. The process according to claim 20, further including the step of oxidizing said porous regions prior to said removing step.

22. An etch stop process comprising the steps of:

providing a SiC layer of a first conductivity type, on top of a layer of SiC of a second conductivity type; and

anodizing the first layer so that the second layer remains inert, to form porous SiC in place of the first layer; and

removing the porous layer.

23. The process according to claim 22, wherein said porous regions are defined photolithographically prior to said anodizing step.

25. A method of fabricating porous SiC comprising the steps of:

placing a wafer of silicon carbide in a electrochemical cell;

electrochemically etching said wafer for a period sufficient to form pores on a exposed surface of said wafer wherein said pores define spacings of less than 1 micron.

26. The method according to claim 25 further including the step of:

illuminating said exposed surface of said wafer with ultraviolet (UV) light.

27. The method according to claim 25, wherein said step of electrochemically etching includes applying an anodic potential to said wafer in said cell.

28. The method according to claim 27, wherein said potential is between 0-3 volts.

29. The method according to claim 25, further including oxidizing porous portions of said wafer after said etching step to convert said porous silicon carbide into silicon dioxide.

30. The method according to claim 29, further including densifying the regions of silicon dioxide.

31. The method according to claim 30, wherein said densifying step comprises annealing said regions of silicon dioxide.

32. The method according to claim 25, wherein a monocrystalline layer of porous silicon carbid, is formed during said etching step.

33. The method according to claim 25, further including the step of passivating a surface of said layer.

34. The method according to claim 33, wherein said passivating step comprises forming a thin insulating layer on the surface of the said porous layer.