Semiconductor process for forming channel layer with passivated covering

• US 5,455,182 A
• Filed: 05/18/1993
• Issued: 10/03/1995
• Est. Priority Date: 11/02/1990
• Status: Expired due to Term

• Current Assignee: Sharp Electronics Corporation (Hon Hai Precision Industry Co., Ltd.), Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nishimoto, Yoshihiro, Kishida, Yoshifumi
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/062,729
• Time in Patent Office: 868 Days
• Field of Search: 437/40, 437/909, 437/101, 437/41, 437/21, 437/968
• US Class Current: 438/165
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: Y10S 438/958 Passivation layer

Abstract

A thin film transistor which includes a first insulating layer, a silicon channel layer formed on the first insulating layer, and a second insulating layer formed on the silicon channel layer, and a passivation layer formed on the first insulating layer and formed successive to and covering the side face of the channel layer between the first and second insulating layers.

Claims

1. A process for fabricating a thin film transistor layer comprising the steps of:

preparing a first insulating layer,

forming a semiconductor layer on the first insulating layer with silicon,

forming a second insulating layer on the semiconductor layer by patterning,

using the second insulating layer as a mask during an oxidation process to form a channel layer from a portion of the semiconductor layer which is positioned below the second insulating layer and oxidizing an unmasked portion of the semiconductor layer to form a passivation layer covering at least one side face of the channel layer;

retaining at least a portion of the second insulation layer over the channel layer; and

forming at least one of a source electrode and a drain electrode over the second insulation layer.

2. A process according to claim 1, wherein the silicon is amorphous silicon.

3. A process according to claim 1, wherein the silicon is polycrystalline silicon.

4. A process according to claim 1, wherein the silicon is monocrystal silicon.

9. A thin transistor according to claim 1, further comprising forming a third insulating layer on the second insulating layer and under at least one of the source electrode and the drain electrode.

10. A process according to claim 1, wherein the second insulating layer has a shape which defines the shape of the channel layer.

11. A process according to claim 1, wherein the second insulating layer is formed of SiN_x.

12. A process according to claim 1, wherein the oxidation process is performed by anodization.

13. A process according to claim 1, wherein a further etching process is performed for removing a part of the passivation layer.

14. A process according to claim 1, wherein the passivation layer is continuous with the channel layer and constantly protects the channel layer during fabrication processes.

5. A process for fabricating a thin film transistor comprising the steps of:

preparing a first insulating layer;

forming a semiconductor layer on the first insulating layer with silicon;

forming a second insulating layer on the semiconductor layer by patterning so as to cover and protect at least a portion of the semiconductor layer;

using the second insulating layer as a mask during an oxidation process and oxidizing an unmasked portion of the semiconductor layer to form a passivation layer covering at least one side face of a channel layer;

retaining at least a portion of the second insulation layer over the channel layer; and

forming at least one of a source electrode and a drain electrode over the second insulation layer.

6. A process according to claim 5, wherein the silicon is amorphous silicon.

7. A process according to claim 5, wherein the silicon is polycrystalline silicon.

8. A process according to claim 5, wherein the silicon is monocrystal silicon.

15. A process according to claim 5, wherein the second insulating layer has a shape which defines the shape of the channel layer.

16. A process according to claim 5, wherein the second insulating layer is formed of SiN_x.

17. A process according to claim 5, wherein the oxidation process is performed by anodization.

18. A process according to claim 5, wherein a further etching process is performed for removing a part of the passivation layer.

19. A process according to claim 5, wherein the passivation layer is continuous with the channel layer and constantly protects the channel layer during fabrication processes.