Late programming mask ROM and process for producing the same

• US 5,455,435 A
• Filed: 11/09/1993
• Issued: 10/03/1995
• Est. Priority Date: 11/09/1993
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Fu, Chien-Chih, Lee, Fong-Chun, Wang, Nan-Chueh, Pao, Shiao-Fen
• Primary Examiner(s): Ngo, Ngan V.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US08/149,847
• Time in Patent Office: 693 Days
• Field of Search: 257/328, 257/329, 257/355
• US Class Current: 257/328
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/40 having the source region and drain region on different levels, e.g. vertical channel

Abstract

A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.

Claims

1. A ROM integrated circuit comprising:

a silicon substrate; and

a plurality of memory cells formed on said silicon substrate, each memory cell including a transistor element and a diode element electrically connected in series, each transistor element having a drain layer, a channel layer, a source layer all stacked on said silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on said silicon substrate;

said gate electrode regions and said upright drain/channel/source structure regions of said transistor elements being alternately arranged in an adjacent fashion along a substantially horizontal direction, and each upright drain/channel/source structure region providing, at two opposite sides, drain/channel/source structures for two transistor elements, which are respectively controlled by two adjacent gate electrodes.

2. The ROM integrated circuit as claimed in claim 1, further comprising a plurality of diode layers formed in said silicon substrate and under said upright drain/channel/source structure regions, said diode elements being formed in combination with said upright drain/channel/source structure regions.

3. The ROM integrated circuit as claimed in claim 2, wherein said mask ROM integrated circuit is programmable by implanting a dopant into the channel layers of designated memory cells.

4. The mask ROM integrated circuit as claimed in claim 3, further comprising a passivation layer formed over said gate electrode regions and said drain/channel/source structure regions, with a plurality of pad openings formed in designated regions.

5. The mask ROM integrated circuit as claimed in claim 2, wherein said mask ROM integrated circuit is programmable by etching to remove at least part of the gate electrode regions of designated memory cells.

6. The mask ROM integrated circuit as claimed in claim 1, further comprising a plurality of diode layers formed on said upright drain/channel/source structure regions, and said diode elements being formed in combination with said upright drain/channel/source structure regions.

7. The mask ROM integrated circuit as claimed in claim 6, wherein said mask ROM integrated circuit is programmable by implanting a dopant into the channel layers of designated memory cells.

8. The mask ROM integrated circuit as claimed in claim 7, further comprising a passivation layer formed over said diode layers and said gate electrode regions, with a plurality of pad openings formed in designated regions.

9. The mask ROM integrated circuit as claimed in claim 6, wherein said mask ROM integrated circuit is programmable by etching to remove at least part of the gate electrode regions of designated memory cells.