Protection circuit against electrostatic discharge using SCR structure

• US 5,455,436 A
• Filed: 05/19/1994
• Issued: 10/03/1995
• Est. Priority Date: 05/19/1994
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Cheng, Wen-Bor
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/246,165
• Time in Patent Office: 502 Days
• Field of Search: 257/110, 257/141, 257/127, 257/355, 257/360, 257/361, 257/362, 257/356, 257/408, 361/58, 361/56, 361/100
• US Class Current: 257/356
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

The output buffer using an LDD NMOS is protected with an SCR at the output pad against electrostatic discharge (ESD). An abrupt (non-LDD) junction NMOS is used as the equivalent npn transistor in the pnpn SCR structure in a dedicated n-well. The non-LDD NMOS has a lower avalanche breakdown voltage than the LDD NMOS buffer, and triggers the SCR to turn on before the avalanche breakdown of the LDD transistor. This non-LDD NMOS lowers the trigger voltage and diverts the ESD current from flowing through the buffer to avoid damage to the buffer.

Besides the n-well for forming the protective SCR, auxiliary n+diffusions and n-wells are placed outside the n-well for to form drains of another non-LDD NMOS, which are connected to the positive power supply. These non-LDD NMOS act as npn transistor and are turned on when high voltage ESD pulses appears at the I/O pad or any power supply terminal to shunt the ESD current to ground, thus avoiding latch-up between the power supply terminals. The output buffer using an LDD NMOS is protected with an SCR at the output pad against electrostatic discharge (ESD). An abrupt (non-LDD) junction NMOS is used as the equivalent npn transistor in the pnpn SCR structure in a dedicated n-well. The non-LDD NMOS has a lower avalanche breakdown and a longer channel length than the LDD NMOS buffer, and triggers the SCR to turn on before the avalanche breakdown of the LDD transistor. This non-LDD NMOS lowers the trigger voltage and diverts the ESD current from flowing through the buffer to avoid damage to the buffer. Besides the n-well for forming the protective SCR, auxiliary n+diffusions and n-wells are placed outside the n-well to form collectors of npn transistors, which are connected to the positive power supply. These npn transistors are turned on when high voltage ESD pulses appear at the I/O pad or any power supply terminal to shunt the ESD current to ground, thus avoiding latch-up between the power supply terminals.

Claims

1. A protection circuit against electrostatic discharge (ESD) for complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) of p-type substrate having n-channel MOS field effect transistors (NMOS) with lightly-doped drain (LDD) and having at least one bonding pad for external connection, comprising:

a first n-well having a heavily-doped n+diffusion and a heavily-doped p+diffusion connected together and to said bonding pad,

a non-LDD NMOS, which does not have a lightly doped drain, having a drain connected to said first n-well, an n+ source connected to the negative terminal of a power supply with a positive terminal and a negative terminal, a gate connected to said source, and a channel having a effective channel length longer than the channel length of said NMOS with lightly-doped drain (LDD NMOS),

said first n-well and said non-LDD NMOS forming a pnpn SCR structure, which turns on when said ESD pulse appears at said bonding pad, with said p+diffusion, said n-well, said p-substrate and said n+source corresponding to said pnpn strusture.

2. A protection circuit against ESD as described in claim 1, wherein said bonding pad is connected to the drain of an LDD NMOS output buffer with a source connected to said negative terminal of said power supply.

3. A protection circuit against ESD as described in claim 1, wherein said non-LDD drain is diffused into said first n-well.

4. A protection circuit against ESD as described in claim 1, wherein said drain of said LDD MNOS is diffused into said first n-well.

5. A protection circuit against ESD as described in claim 1, wherein said non-LDD NMOS has a gate oxide as thin as the gate oxide of said LDD NMOS.

6. A protection circuit against ESD as described in claim 1, wherein said non-LDD NMOS has a gate oxide thicker than the gate oxide of said LDD NMOS.

7. A protection circuit against ESD as described in claim 1, wherein there is a second n+diffusion, which is diffused outside the non-LDD NMOS away from said first n-well and connected to said positive terminal of said power supply, and forms a first abrupt junction npn bipolar transistor structure corresponding to the second n+diffusion as collector, the p-substrate as base and the n+source of the non-LDD NMOS as emitter.

8. A protection circuit against ESD as described in claim 7, wherein an oxide with a thickness equal to the gate oxide of the LDD NMOS is interposed over the p-substrate and between said second n+ diffusion and said n+source of said non-LDD NMOS.

9. A protection circuit ESD as described in claim 7, wherein an oxide with a thickness thicker than the gate oxide of the LDD NMOS is interposed over the p-substrate and between said second n+diffusion and said n+source of said non-LDD NMOS.

10. A protection circuit against ESD as described in claim 7, wherein there is a second n-well diffused inside said second n+diffusion.

11. A protection circuit against ESD as described in claim 7, wherein there is a third n+diffusion, which is placed outside said first n-well and connected to said positive terminal of said power supply, and forms a second abrupt junction npn bipolar transistor structure with said third n+diffusion as collector, the p-substrate as base and said n-well as emitter.

12. A protection circuit against ESD as described in claim 11, wherein the oxide covering said base is as thin as the thickness of the LDD NMOS.

13. A protection circuit against ESD as described in claim 11, wherein the oxide covering said base is thicker than the gate oxide of the LDD NMOS.

14. A protection circuit against ESD as described in claim 11, wherein there is a third n-well diffused inside said third n+diffusion.

15. A protection circuit against ESD as described in claim 1, wherein the n-type and p-type semiconductivity types are reversed.

16. A protection circuit against ESD as described in claim 8, wherein a polysilicon gate lager is deposited over said oxide which is interposed over said p-substrate and between said second n+diffusion and said n+source diffusion of said said non-LDD NMOS, and connected to said negative terminal of said power supply.