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Protection circuit against electrostatic discharge using SCR structure

  • US 5,455,436 A
  • Filed: 05/19/1994
  • Issued: 10/03/1995
  • Est. Priority Date: 05/19/1994
  • Status: Expired due to Term
First Claim
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1. A protection circuit against electrostatic discharge (ESD) for complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) of p-type substrate having n-channel MOS field effect transistors (NMOS) with lightly-doped drain (LDD) and having at least one bonding pad for external connection, comprising:

  • a first n-well having a heavily-doped n+diffusion and a heavily-doped p+diffusion connected together and to said bonding pad,a non-LDD NMOS, which does not have a lightly doped drain, having a drain connected to said first n-well, an n+ source connected to the negative terminal of a power supply with a positive terminal and a negative terminal, a gate connected to said source, and a channel having a effective channel length longer than the channel length of said NMOS with lightly-doped drain (LDD NMOS),said first n-well and said non-LDD NMOS forming a pnpn SCR structure, which turns on when said ESD pulse appears at said bonding pad, with said p+diffusion, said n-well, said p-substrate and said n+source corresponding to said pnpn strusture.

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