Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby

• US 5,455,455 A
• Filed: 08/20/1993
• Issued: 10/03/1995
• Est. Priority Date: 09/14/1992
• Status: Expired due to Term

• Current Assignee: DigitalOptics Corporation Europe Limited (Adeia Inc.)
• Original Assignee: Peirre Badehi
• Inventors: Badehi, Peirre
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): BROWN, PETER T
• Application Number:
  US07/962,222
• Time in Patent Office: 774 Days
• Field of Search: 437/226, 437/227, 437/974, 437/208, 257/690, 257/723, 257/734, 257/693, 257/698, 257/787, 257/793, 257/758, 257/759, 257/760
• US Class Current: 257/690
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer, each of the integrated circuits including a multiplicity of pads and thereafter slicing the wafer, thereby to define a plurality of integrated circuit elements, and wherein the step of slicing exposes sectional surfaces of the multiplicity of pads. Apparatus for carrying out the method and integrated circuit devices are also described.

Claims

1. A method of producing packaged integrated circuit devices comprising the steps of:

producing a plurality of integrated circuits on a wafer having first and second planar surfaces, each of the integrated circuits comprising a multiplicity of pads;

separating the integrated circuits from each other so as to define edges thereof and generally surrounding said integrated circuits on said edges and on said first and second planar surfaces with generally the same protective sealant and waferwise attaching to said protective sealant adjacent both of said surfaces a layer of protective material, thereby producing a waferwise sandwich; and

thereafter slicing the waferwise sandwich, thereby to define a plurality of prepackaged integrated circuit devices.

2. A method according to claim 1 and wherein the step of slicing exposes sectional surfaces of said multiplicity of pads.

3. A method according to claim 2 and wherein the step of slicing cuts pads associated with a pair of adjacent integrated circuits, thereby to simultaneously define electrical contact regions for both of said pair of adjacent integrated circuits.

4. A method according to claim 1 and also comprising the steps of providing a conductive layer over sliced edges of the integrated circuits and electrically separating portions of the conductive layer communicating with separate ones of said multiplicity of pads.

5. A method according to claim 4 and wherein an electrical insulative layer is present along the sliced edges of said integrated circuits before the step of providing a conductive layer.

6. A method according to claim 4 and wherein said step of providing a conductive layer comprises forming a conductive coating over non-edge portions of the integrated circuit.

7. A method according to claim 1 and wherein said protective sealant comprises epoxy.

8. A method according to claim 1 and wherein a thermal contact to a heat sink is formed on at least one outer planar surface of said integrated circuit devices.

9. A method according to claim 1 and also comprising the step of providing an integrally formed ground plane in said integrated circuit devices.

10. A method according to claim 1 and wherein a plurality of wafers bearing integrated circuits are joined together in a stacked arrangement to provide multi-layer integrated circuit devices.

11. A method according to claim 1 and also comprising the step of mounting the integrated circuit devices along their edges onto a mounting element.

12. A method according to claim 1 and wherein said protective material is transparent to radiation which is used for erasing EPROM devices.

13. A method according to claim 1 and also comprising anti-corrosion treatment of electrical contacts of said integrated circuit devices including exposed pad edges.

14. An integrated circuit device constructed according to the method of claim 1.

15. An integrated circuit device according to claim 14 and wherein said integrated circuit device includes a plurality of semiconductor portions which are mutually isolated from each other.

16. An integrated circuit device according to claim 14 and comprising at least one semiconductor element which is mechanically and electrically isolated from the exterior surface of the device.

17. An integrated circuit device according to claim 1 and also comprising an integrally formed thermal contact to a heat sink on an outer planar surface of the device.

18. An integrated circuit device according to claim 1 and also comprising an integrally formed ground plane.

19. An integrated circuit device according to claim 14 and wherein conductive strips are formed on the outside surface of said integrated circuit device for interconnecting said exposed sections of conductive pads at a plurality of edges.

20. A method of producing packaged integrated circuit devices comprising the steps of:

producing a plurality of integrated circuits having planar surfaces on a wafer, each of the integrated circuits comprising a multiplicity of pads;

separating the integrated circuits from each other so as to define edges thereof and generally surrounding said integrated circuits on their edges and on their planar surfaces with generally the same protective sealant, thereby producing a waferwise sandwich; and

thereafter slicing the waferwise sandwich, thereby to define a plurality of prepackaged integrated circuit elements, and wherein the step of slicing exposes sectional surfaces of said multiplicity of pads.

21. A method according to claim 20 and wherein the step of slicing cuts a plurality of pads including some which communicate with one of a pair of adjacent integrated circuits and others which communicate with another of the pair of adjacent integrated circuits, thereby to define electrical contact regions for both of said pair of adjacent integrated circuits.

22. A method according to claim 20 and wherein said protective sealant comprises epoxy.

23. A method of producing packaged integrated circuit devices comprising the steps of:

producing a plurality of integrated circuits on a wafer having first and second planar surfaces, each of the integrated circuits comprising a multiplicity of pads;

separating the integrated circuits from each other so as to define edges thereof and generally surrounding said integrated circuits on said edges with epoxy and waferwise bonding onto both of said surfaces a layer of protective material, thereby producing a waferwise sandwich; and

thereafter slicing the waferwise sandwich, thereby to define a plurality of prepackaged integrated circuit devices, and wherein prior to said slicing step, the integrated circuits are surrounded on their planar surfaces by said layer of protective material and on their edges by said epoxy.

24. A method according to claim 23 and wherein the step of slicing exposes sectional surfaces of said multiplicity of pads.

25. A method according to claim 24 and wherein the step of slicing cuts pads associated with a pair of adjacent integrated circuits, thereby to simultaneously define electrical contact regions for both of said pair of adjacent integrated circuits.

26. A method according to claim 23 and wherein the step of slicing cuts a plurality of pads including some which communicate with one of a pair of adjacent integrated circuits and others with communication with another of the pair of adjacent integrated circuits, thereby to define electrical contact regions for both of said pair of adjacent integrated circuits.

27. A method according to claim 23 and also comprising the steps of providing a conductive layer over sliced edges of the packaged integrated circuits and electrically separating portions of the conductive layer communicating with separate ones of said multiplicity of pads.

28. A method according to claim 27 and wherein an electrical insulative layer is present along the sliced edges of said packaged integrated circuits before the step of providing a conductive layer.

29. A method according to claim 27 and wherein said step of providing a conductive layer comprises forming a conductive coating also over non-edge portions of the packaged integrated circuit.

30. A method according to claim 23 and wherein said separating step includes the steps of scribing and subsequent etching of the wafer.

31. A method according to claim 23 and wherein said slicing step is carried out at locations whereby the silicon substrate is not exposed at the sliced edges of the resulting packaged integrated circuits.

32. A method according to claim 23 and wherein a thermal contact to a heat sink is formed on at least one outer planar surface of said packaged integrated circuit devices.

33. A method according to claim 23 and also comprising the step of providing an integrally formed ground plane in said integrated circuit devices.

34. A method according to claim 23 and wherein a plurality of wafers bearing integrated circuits are joined together in a stacked arrangement to provide packaged multi-layer integrated circuit devices.

35. A method according to claim 23 and also comprising the step of mounting the packaged integrated circuit devices along their edges onto a mounting element.

36. A method according to claim 23 and wherein said protective material is transparent to radiation which is used for erasing EPROM devices.

37. A method according to claim 23 and also comprising anti-corrosion treatment of electrical contacts of said integrated circuit devices including exposed pad edges.

38. A method of producing packaged semiconductor devices comprising the steps of:

producing a plurality of semiconductor elements on a wafer having first and second planar surfaces, each of the semiconductor elements comprising a multiplicity of pads;

separating the integrated circuits from each other so as to define edges thereof and generally surrounding said semiconductor elements at said edges and said first and second planar surfaces with generally the same protective sealant and waferwise attaching to said protective sealant adjacent both of said surfaces a layer of protective material, thereby producing a waferwise sandwich;

thereafter slicing the waferwise sandwich, thereby to define a plurality of prepackaged semiconductor element devices, each comprising a mechanically protective and electrically insulative package having a plurality of exposed cross-sections of said pads exposed at edges thereof; and

providing electrical connections between said exposed cross-sections and external circuitry.

39. A method according to claim 38 and wherein said protective sealant comprises epoxy.

40. An integrated circuit device comprising:

a packaged integrated circuit assembly comprising a semiconductor substrate having at least first and second patterned metal layers formed over said semiconductor substrate, defining therewith semiconductor circuit elements having edges, said semiconductor substrate being generally surrounded along its edges and over said first and second patterned metal layers by generally the same protective sealant, said integrated circuit assembly having top and bottom surfaces formed of electrically insulative and mechanically protective material and electrically insulative edge surfaces defined by said protective sealant and having exposed sections of conductive pads formed by at least one of said first and second patterned metal layers.

41. An integrated circuit device according to claim 40 and wherein said integrated circuit assembly comprises a plurality of semiconductor chips bonded together in stacked arrangement.

42. An integrated circuit device according to claim 41 and wherein said plurality of semiconductor chips are mutually insulated from each other within said integrated circuit assembly.

43. An integrated circuit device according to claim 40 and also comprising conductive strips formed on the outer surface of the integrated circuit device and in electrical communication with said exposed sections of conductive pads.

44. An integrated circuit device according to claim 43 and wherein said conductive strips extend along the edges of said integrated circuit device.

45. An integrated circuit device according to claim 44 and wherein said conductive strips extend also to planar surfaces of said integrated circuit device.

46. An integrated circuit device according to claim 40 and wherein conductive strips are formed on the outside surface of said integrated circuit device for interconnecting said exposed sections of conductive pads of a plurality of dies, thereby providing electrical interconnection therebetween.