CMOS buffer circuit with controlled current source

• US 5,455,527 A
• Filed: 09/17/1993
• Issued: 10/03/1995
• Est. Priority Date: 09/18/1992
• Status: Expired due to Term

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Zibert, Martin, Murphy, Brian
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/123,647
• Time in Patent Office: 746 Days
• Field of Search: 307/475, 307/473, 307/451, 307/443, 307/448, 307/481, 326/83, 326/87, 326/58, 326/121, 326/99, 326/34, 326/31
• US Class Current: 326/83
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

An integrated buffer circuit configuration has two inverters which are mutually connected in series. A circuit node lies between the two inverters. At least the first inverter is a CMOS inverter for an input signal IN. The CMOS inverter has an n-channel transistor which is connected to a first supply potential. The source of a p-channel transistor is connected with a constant current source. A first enable transistor is connected between the n-channel transistor of the first inverter and the circuit node. A second enable transistor is connected in parallel to the configuration formed by the constant current source and the p-channel transistor of the first inverter. The gates of the enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS-transistor may function as the constant current source. The MOS-transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS-transistor is conducting.

Claims

1. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input, wherein said constant current source includes an MOS-transistor connected between said source of said second transistor of said first inverter and a second supply potential, said MOS-transistor being electrically conductive during an operation of the buffer circuit and having a gate receiving a reference potential during an operation of the buffer circuit, said reference potential having a value different from said second supply potential by a constant amount; and

means for generating said reference potential, said generating means including resistance means and diode means;

said resistance means being a potentiometer-type resistor having a first resistor part and a second resistor part;

said first and second resistor parts, at ends facing one another, being connected to said gate of said MOS-transistor and forming a potential pickup of said resistance means;

said diode means being connected between said first resistor part and said second supply potential; and

said second resistor part being connected to said first supply potential.

2. The integrated buffer circuit according to claim 1, wherein said diode means are one of a transistor switched as a diode and a p-n junction diode.

3. The integrated buffer circuit according to claim 1, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

4. The integrated buffer circuit according to claim 1, wherein said first and second enable transistors are of mutually opposite channel types.

5. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input, wherein said constant current source includes an MOS- transistor connected between said source of said second transistor of said first inverter and a second supply potential, said MOS-transistor being electrically conductive during an operation of the buffer circuit and having a gate receiving a reference potential during an operation of the buffer circuit, said reference potential having a value different from said second supply potential by a constant amount; and

means for generating said reference potential, said generating means comprising first and second resistors and diode means;

said first and second resistors being mutually connected with one another and said gate of said MOS-transistor;

said diode means being connected between said first resistor and said second supply potential; and

said second resistor being connected to said first supply potential.

6. The integrated buffer circuit according to claim 5, wherein said diode means are one of a transistor switched as a diode and a p-n junction diode.

7. The integrated buffer circuit according to claim 5, wherein said first and second enable transistors are of mutually opposite channel types.

8. The integrated buffer circuit according to claim 5, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

9. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input, wherein said constant current source includes an MOS- transistor connected between said source of said second transistor of said first inverter and a second supply potential, said MOS-transistor being electrically conductive during an operation of the buffer circuit and having a gate receiving a reference potential during an operation of the buffer circuit, said reference potential having a value different from said second supply potential by a constant amount; and

a capacitor connected between said input of said first inverter and said gate of said MOS-transistor.

10. The integrated buffer circuit according to claim 9, wherein said first and second enable transistors are of mutually opposite channel types.

11. The integrated buffer circuit according to claim 9, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

12. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input, wherein said constant current source includes

an MOS-transistor connected between said source of said second transistor of said first inverter and a second supply potential, said MOS-transistor being electrically conductive during an operation of the buffer circuit and having a gate receiving a reference potential during an operation of the buffer circuit, said reference potential having a value different from said second supply potential by a constant amount; and

a first capacitor connected between said gate of said MOS-transistor and said first supply potential, and a second capacitor connected between said input of said first inverter and said gate of said MOS-transistor.

13. The integrated buffer circuit according to claim 12, wherein at least one of said first and second capacitors is an MOS varactor.

14. The integrated buffer circuit according to claim 12, wherein said first and second enable transistors are of mutually opposite channel types.

15. The integrated buffer circuit according to claim 12, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

16. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input; and

a hysteresis transistor having a channel path connected between said circuit node and said first supply potential, and having a gate connected to said output of said second inverter.

17. The integrated buffer circuit according to claim 16, wherein said hysteresis transistor is an n-channel transistor.

18. The integrated buffer circuit according to claim 16, wherein said hysteresis transistor has a saturation current less than a current of said constant current source.

19. The integrated buffer circuit according to claim 16, wherein said first and second enable transistors are of mutually opposite channel types.

20. The integrated buffer circuit according to claim 16, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

21. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input, wherein said constant current source includes an MOS- transistor connected between said source of said second transistor of said first inverter and a second supply potential, said MOS-transistor being electrically conductive during an operation of the buffer circuit and having a gate receiving a reference potential during an operation of the buffer circuit, said reference potential having a value different from said second supply potential by a constant amount; and

a hysteresis transistor having a channel path connected between said circuit node and said second supply potential, and having a gate connected to said output of said second inverter.

22. The integrated buffer circuit according to claim 21, wherein said hysteresis transistor is a p-channel transistor.

23. The integrated buffer circuit according to claim 21, wherein said hysteresis transistor has a channel with a channel width and channel length, said channel length and said channel width having a ratio being less than a ratio of a channel width to a channel length of a channel of said first transistor of said first inverter.

24. The integrated buffer circuit according to claim 21, wherein said first and second enable transistors are of mutually opposite channel types.

25. The integrated buffer circuit according to claim 21, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

26. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input; and

a first hysteresis transistor having a channel path connected between said circuit node and said first supply potential, and having a gate connected to said output of said second inverter, and a second hysteresis transistor having a channel path connected between said circuit node and said second supply potential, and having a gate connected to said output of said second inverter.

27. The integrated buffer circuit according to claim 26, wherein said first hysteresis transistor is an n-channel transistor and said second hysteresis transistor is a p-channel transistor.

28. The integrated buffer circuit according to claim 26, wherein said first and second enable transistors are of mutually opposite channel types.

29. The integrated buffer circuit according to claim 26, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.

30. An integrated buffer circuit, comprising:

a first inverter having an input for receiving an input signal, and a constant current source;

a second inverter connected in cascade with said first inverter, said second inverter having an output issuing an output signal of the buffer circuit, and a circuit node connected between said first and second inverters;

said first inverter being a CMOS-inverter including first and second transistors, said first and second transistors being connected in series across said circuit node and being of a mutually opposite channel type;

said first and second transistors of said first inverter having electrically connected gates forming said input of said first inverter;

said first transistor of said first inverter having a source connected to a first supply potential;

said second transistor of said first inverter having a source connected to said constant current source;

said first transistor having a drain;

a first enable transistor having a current-carrying path connected between said drain of said first transistor and said circuit node;

a second enable transistor having a current-carrying path connected in parallel to a path formed by said constant current source and said second transistor of said first inverter;

an enable input of the buffer circuit, said gates of said first and second enable transistors being connected to said enable input; and

wherein said first and second enable transistors are of the same channel type, and including a third inverter connected between said enable input and a gate of one of said first and second enable transistors.

31. The integrated buffer circuit according to claim 30, including a capacitor connected between said gate of said MOS-transistor and said first supply potential.