Modified bang-bang phase detector with ternary output

• US 5,455,540 A
• Filed: 10/26/1994
• Issued: 10/03/1995
• Est. Priority Date: 10/26/1994
• Status: Expired due to Term

• Current Assignee: Dot Assets No 12 LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Bertrand J.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/329,277
• Time in Patent Office: 342 Days
• Field of Search: 331/1 A, 331/25, 327/12, 329/303, 329/310-313, 360/41, 360/51, 375/327, 375/328, 375/375, 375/376
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the dock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the dock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the dock signal.

Claims

1. A method for controlling a dock generator comprising:

generating a dock signal;

receiving a data signal from an external circuit;

generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal;

generating a second signal when said transition edge of said clock signal occurs before said transition edge of said data signal; and

generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

2. The method of claim 1 further comprising:

accelerating said dock signal in response to said first signal;

delaying

said dock signal in response to said second signal; and

maintaining said dock signal in response to said third signal.

3. The method of claim 2 wherein accelerating said clock signal in response to said first signal comprises increasing frequency of said clock signal and wherein delaying said clock signal in response to said second signal comprises decreasing frequency of said dock signal.

4. The method of claim 2 wherein accelerating said dock signal in response to said first signal comprises shifting in a phase of said clock signal and wherein delaying said dock signal in response to said second signal comprises shifting out said phase of said clock signal.

5. The method of claim 1 further comprising:

generating a first signal state when said transition edge of said data signal occurs; and

generating a second signal state when said data signal remains in said same signal state for at least two transition edges of a same type of said clock signal.

6. The method of claim 1 further comprising:

generating a first signal state when said transition edge of said data signal occurs before said transition edge of said clock signal; and

generating a second signal state when said transition edge of said data signal occurs after said transition edge of said clock signal.

7. The method of claim 1 wherein said transition edges of a same type of said dock signal are rising transition edges.

8. The method of claim 1 wherein said transition edges of a same type of said dock signal are falling transition edges.

9. A phase detector for indicating phase comprising:

a data input allowing said phase detector to receive a data signal from a data signal source;

a dock input allowing said phase detector to receive a clock signal from a dock signal source;

first circuitry coupled to said data input and said clock input operable to indicate a transition edge of said data signal; and

second circuitry coupled to said data input and said dock input operable to indicate a position of said transition edge of said data signal relative to a transition edge of said dock signal.

10. The phase detector of claim 9 wherein said first circuitry is operable to generate a first signal state when said phase detector receives said transition edge of said data signal and operable to generate a second signal state when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

11. The phase detector of claim 9 wherein said second circuitry is operable to generate a first signal state when said transition edge of said data signal occurs before said transition edge of said clock signal and operable to generate a second signal state when said transition edge of said data signal occurs after said transition edge of said clock signal.

12. The phase detector of claim 9 further comprising:

third circuitry coupled to said first circuitry and said second circuitry operable to generate a first signal when said transition edge of said clock signal occurs after said transition edge of said data signal, wherein said third circuitry is operable to generate said second signal when said transition edge of said clock signal occurs before said transition edge of said data signal, and wherein said third circuitry is operable to generate said third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said dock signal.

13. The phase detector of claim 12 wherein said first signal is a first voltage potential, wherein said second signal is a second voltage potential and wherein said third signal is a third voltage potential.

14. The phase detector of claim 11 further comprising:

third circuitry coupled to said first circuitry and said second circuitry operable to generate a first signal when said first circuitry and said second circuitry generate a first signal state, wherein said third circuitry is operable to generate a second signal when said first circuitry generates said first signal state and said second circuitry generates a second signal state, and wherein said third circuitry is operable to generate a third signal when said first circuitry generates said second signal state.

15. The phase detector of claim 9 further comprising:

a delay circuit coupled to said data input and said second circuitry operable to delay receipt of said data signal by said second circuitry.

16. The phase detector of claim 15 further comprising:

a data output coupled to said delay circuit allowing said phase detector to output a delayed data signal.

17. An apparatus for controlling a dock generator comprising:

means for generating a clock signal;

means for receiving a data signal from an external circuit;

means for generating a first signal when a transition edge of said clock signal occurs after a transition edge of said data signal;

means for generating a second signal when said transition edge of said dock signal occurs before said transition edge of said data signal; and

means for generating a third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal.

18. The apparatus of claim 17 further comprising:

means for indicating when said transition edge of said data signal occurs; and

means for indicating a position of said transition edge of said data signal relative to said transition edge of said clock signal.

19. A phase-locked loop circuit comprising:

a clock generator operable to accelerate a clock signal in response to a first signal, operable to delay said dock signal in response to a second signal, and operable to maintain said clock signal in response to a third signal;

a phase detector coupled to said clock generator operable to generate said first signal when a transition edge of said dock signal occurs after a transition edge of a data signal, wherein said phase detector is operable to generate said second signal when said transition edge of said dock signal occurs before said transition edge of said data signal, and wherein said phase detector is operable to generate said third signal when said data signal remains in a same signal state for at least two transition edges of a same type of said clock signal; and

a data input coupled to said phase detector allowing said phase detector to receive said data signal from an external circuit.

20. The circuit of claim 19 wherein said clock generator is a voltage controlled oscillator.

21. The circuit of claim 19 wherein said clock generator is operable to accelerate said dock signal by increasing frequency of said dock signal and is operable to delay said dock signal by decreasing frequency of said dock signal.

22. The circuit of claim 19 wherein said dock generator is operable to accelerate said clock signal by shifting in a phase of said dock signal and is operable to delay said clock signal by shifting out said phase of said dock signal.

23. The circuit of claim 19 wherein said first signal is a first voltage potential, wherein said second signal is a second voltage potential and wherein said third signal is a third voltage potential.

24. The circuit of claim 19 wherein said transition edge of said dock signal is a rising transition edge.

25. The circuit of claim 19 wherein said transition edge of said clock signal is a falling transition edge.

26. The circuit of claim 19 wherein said transition edges of a same type are rising transition edges of said clock signal.

27. The circuit of claim 19 wherein said transition edges of a same type are falling transition edges of said clock signal.