Computer design system for mapping a logical hierarchy into a physical hierarchy

• US 5,455,775 A
• Filed: 01/25/1993
• Issued: 10/03/1995
• Est. Priority Date: 01/25/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Huber, Gary D., Magryta, Romuald, Lichaa, Harry
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/009,484
• Time in Patent Office: 981 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 364/402, 364/800, 395/500, 395/600, 395/900, 395/115, 361/393, 361/380, 361/385
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A computer design system is used to map a logical hierarchy corresponding to the logical functions of an electronic system into a physical hierarchy corresponding to the physical positioning of the actual electronic components which will implement the logical functions of the system. The logical hierarchy contains several levels of logical entities connected by signals, and the physical hierarchy contains physical packages corresponding to electronic components, such as integrated circuits. The mapping is accomplished by designating partition group assertions (PGAs) for each of the logical entities in the logical hierarchy. Each PGA corresponds to one of the physical packages in the physical hierarchy. Each entity is grouped by common PGA designation, and each signal of each entity is classified as external, if the signal connects entities located on different physical packages, or internal, if the signal connects entities located on the same physical package. The physical hierarchy for the electronic system is generated using lists of these logical entity groupings and signal classifications. An advantage of the present invention is that partitioning of a logical design into a physical design is done automatically.

Claims

1. A method for designing an electronic device using a digital computer wherein a logical hierarchy comprising logical entities interconnected by signals is mapped into a physical hierarchy comprising physical packages, comprising the steps of:

designating partition group assertions for each of said logical entities, each of said partition group assertions corresponding to one of said physical packages;

tracing the signals for each of said logical entities using said computer; and

classifying each of said signals as either external or internal responsive to said tracing, said external classification corresponding to a signal connecting logical entities located on different physical packages and said internal classification corresponding to a signal connecting logical entities located on the same physical package.

2. The method according to claim 1 further comprising the step of providing a first representation of the physical interconnections of said physical packages, said physical interconnections corresponding to said external signals.

3. The method according to claim 2 further comprising the step of providing a second representation for each of said physical packages of the logical entities and interconnecting external and internal signals located thereon.

4. The method according to claim 2 further comprising the step of flattening said logical hierarchy into a logical representation consisting of primitive entities.

5. The method according to claim 4 further comprising the step of storing a list for each of said physical packages indicating which of said primitive entities are physically located thereon.

6. The method according to claim 1 wherein said step of designating partition group assertions comprises designating at least one of said assertions by representation through a parent entity.

7. The method according to claim 1 further comprising the steps of:

providing a physical constraints file corresponding to at least one of said physical packages;

determining a physical attribute for at least one of said physical packages and corresponding to said physical hierarchy; and

comparing said physical attribute to said physical constraints file.

8. A method for designing an electronic device using a digital computer having a memory wherein a logical hierarchy comprising parent and primitive logical entities interconnected by signals and stored in said memory, said logical hierarchy representing logical functions corresponding to said electronic device, is mapped into a physical hierarchy comprising physical packages and stored in said memory, comprising the steps of:

designating partition group assertions for each of said primitive entities, each of said partition group assertions corresponding to one of said physical packages;

flattening said logical hierarchy into a logical representation consisting of primitive entities;

storing a list in said memory for each of said physical packages indicating which of said primitive entities are physically located thereon;

tracing the signals for each of said primitive entities with said computer using said list for each of said physical packages;

classifying each of said signals as either external or internal responsive to said tracing, said external classification corresponding to a signal connecting primitive entities located on different physical packages and said internal classification corresponding to a signal connecting primitive entities located on the same physical package; and

generating said physical hierarchy of said physical packages, said physical hierarchy providing a first representation of the physical interconnections of said physical packages, said physical interconnections corresponding to said external signals, and a second representation for each of said physical packages indicating the primitive entities and interconnecting external and internal signals located thereon.

9. The method according to claim 8 further comprising the steps of:

providing a physical constraints file corresponding to at least one of said physical packages;

determining a physical attribute for at least one of said physical packages and corresponding to said physical hierarchy; and

comparing said physical attribute to said physical constraints file.

10. The method according to claim 9 wherein said step of determining a physical attribute comprises determining a physical attribute corresponding to said first representation.

11. The method according to claim 9 wherein said step of determining a physical attribute comprises determining a physical attribute corresponding to said second representation.

12. The method according to claim 9 further comprising the step of generating a compliance report for at least one of said physical packages in response to said step of comparing.

13. The method according to claim 8 wherein said step of designating partition group assertions comprises designating partition group assertions using an interactive graphics terminal.

14. The method according to claim 8 wherein said step of designating partition group assertions comprises designating a partition group assertion for at least one of said primitive entities by representation through a parent entity thereof.

15. The method according to claim 8 wherein said first representation comprises a graphical representation.

16. The method according to claim 8 wherein said second representation comprises a graphical representation.

17. A digital computer for designing an electrical device, said computer having a central processing unit, a memory, and an input/output system, comprising:

first storage means for storing a logical hierarchy comprising logical entities interconnected by signals;

second storage means for storing a physical hierarchy comprising physical packages and physical interconnections therebetween;

means for designating partition group assertions for each of said logical entities, each of said partition group assertions corresponding to one of said physical packages;

means for tracing the signals for each of said logical entities; and

means for classifying each of said signals as either external or internal responsive to said tracing, said external classification corresponding to a signal connecting logical entities located on different physical packages and said internal classification corresponding to a signal connecting logical entities located on the same physical package.

18. The computer of claim 17 further comprising means for providing a first representation of the physical interconnections of said physical packages, said physical interconnections corresponding to said external signals, and a second representation for each of said physical packages indicating the primitive entities and interconnecting external and internal signals located thereon.

19. The computer of claim 18 further comprising means for flattening said logical hierarchy into a logical representation consisting of primitive entities.

20. The computer of claim 18 wherein said means for designating partition group assertions comprises means for designating at least one of said assertions by representation through a parent entity.

21. The computer of claim 17 further comprising:

third storage means for storing a physical constraints file corresponding to at least one of said physical packages;

means for determining a physical attribute for at least one of said physical packages and corresponding to said physical hierarchy; and

means for comparing said physical attribute to said physical constraints file.