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Semiconductor memory with improved redundant sense amplifier control

  • US 5,455,798 A
  • Filed: 02/22/1994
  • Issued: 10/03/1995
  • Est. Priority Date: 01/31/1992
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising a memory, said integrated circuit comprising:

  • a plurality of primary memory cells, arranged in a primary array;

    means for accessing a primary memory cell responsive to an address signal presented thereto;

    a redundant memory array comprising a plurality of redundant memory cells;

    a redundant decoder, for selecting a redundant memory cell responsive to an address signal presented thereto corresponding to a programmed value in said redundant decoder;

    redundant read means for sensing the state of a selected redundant memory cell and communicating the same to an output of the memory, said redundant read means having a control input coupled to receive an enable signal;

    means for generating an initiate pulse responsive to a memory cycle signal indicating that a memory access is to be initiated;

    an enable circuit, for generating said enable signal responsive to the initiation of a memory access cycle, comprising;

    a leading edge circuit, having an input coupled to the output of said generating means and having an output for presenting a control signal for a delay period responsive to receiving said initiate pulse;

    a match circuit, having an input coupled to the output of said redundant decoder, and having an output for presenting a match signal responsive to said redundant decoder indicating that the address signal received thereby corresponds to a programmed value therein; and

    enable logic, having inputs coupled to receive said control signal and said match signal, and having an output for generating said enable signal responsive to receipt of either said control signal or said match signal.

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