Semiconductor memory with improved redundant sense amplifier control
First Claim
1. An integrated circuit comprising a memory, said integrated circuit comprising:
- a plurality of primary memory cells, arranged in a primary array;
means for accessing a primary memory cell responsive to an address signal presented thereto;
a redundant memory array comprising a plurality of redundant memory cells;
a redundant decoder, for selecting a redundant memory cell responsive to an address signal presented thereto corresponding to a programmed value in said redundant decoder;
redundant read means for sensing the state of a selected redundant memory cell and communicating the same to an output of the memory, said redundant read means having a control input coupled to receive an enable signal;
means for generating an initiate pulse responsive to a memory cycle signal indicating that a memory access is to be initiated;
an enable circuit, for generating said enable signal responsive to the initiation of a memory access cycle, comprising;
a leading edge circuit, having an input coupled to the output of said generating means and having an output for presenting a control signal for a delay period responsive to receiving said initiate pulse;
a match circuit, having an input coupled to the output of said redundant decoder, and having an output for presenting a match signal responsive to said redundant decoder indicating that the address signal received thereby corresponds to a programmed value therein; and
enable logic, having inputs coupled to receive said control signal and said match signal, and having an output for generating said enable signal responsive to receipt of either said control signal or said match signal.
0 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder associated with each column, each of which includes a set of address fuses into which an address is programmed, responsive to which its associated redundant column is to be selected. A plurality of redundant sense amplifiers are each associated with selected redundant columns, and are each controlled to begin the sense operation prior to propagation of the address signal through the redundant column decoders and summing circuitry. In the event that the received memory address does not match any of the programmed values in the redundant column decoders associated with a redundant sense amplifier, the sense operation is terminated. In this way, the sense operation is not delayed by the additional delay required for redundant decoding and propagation of the redundant address signals, and thus the access time penalty for accessing a redundant memory cell is much reduced or eliminated. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each associated redundant column decoder, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.
-
Citations
17 Claims
-
1. An integrated circuit comprising a memory, said integrated circuit comprising:
-
a plurality of primary memory cells, arranged in a primary array; means for accessing a primary memory cell responsive to an address signal presented thereto; a redundant memory array comprising a plurality of redundant memory cells; a redundant decoder, for selecting a redundant memory cell responsive to an address signal presented thereto corresponding to a programmed value in said redundant decoder; redundant read means for sensing the state of a selected redundant memory cell and communicating the same to an output of the memory, said redundant read means having a control input coupled to receive an enable signal; means for generating an initiate pulse responsive to a memory cycle signal indicating that a memory access is to be initiated; an enable circuit, for generating said enable signal responsive to the initiation of a memory access cycle, comprising; a leading edge circuit, having an input coupled to the output of said generating means and having an output for presenting a control signal for a delay period responsive to receiving said initiate pulse; a match circuit, having an input coupled to the output of said redundant decoder, and having an output for presenting a match signal responsive to said redundant decoder indicating that the address signal received thereby corresponds to a programmed value therein; and enable logic, having inputs coupled to receive said control signal and said match signal, and having an output for generating said enable signal responsive to receipt of either said control signal or said match signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of operating a memory in an integrated circuit, said memory including primary and redundant memory cells, a redundant decoder into which a memory address may be programmed responsive to receipt of which a redundant memory cell is to be accessed instead of a primary memory cell, and a redundant read circuit for reading the state of an accessed redundant memory cell and communicating the same externally from the memory, said redundant read circuit dynamically controlled by a read enable signal, comprising:
-
responsive to a memory cycle signal indicating initiation of a memory access, generating said read enable signal to said redundant read circuit; comparing a received memory address with the programmed address in said redundant decoder; after said generating step, terminating said read enable signal responsive to said comparing step indicating that the received memory address does not match the programmed address. - View Dependent Claims (15, 16, 17)
-
Specification