Dual dynamic sense amplifiers for a memory array

• US 5,455,802 A
• Filed: 12/22/1992
• Issued: 10/03/1995
• Est. Priority Date: 12/22/1992
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US07/995,581
• Time in Patent Office: 1,015 Days
• Field of Search: 365/233, 365/230.08, 365/189.01, 365/201, 365/207, 365/203, 365/208, 365/189.05, 365/189.07, 365/190, 365/196, 307/530, 307/355, 326/51, 326/57
• US Class Current: 365/233.11
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A method and circuit for reading a memory array by utilizing dual dynamic sense amplifiers. A first and a second dynamic sense amplifier are connected to an input line and complementary input line. A latch and a clocking circuit are also connected to the two dynamic sense amplifiers. Initially, an equilibrating signal is input into both sense amplifiers. A first clocking signal and a first isolating signal are then input into the first dynamic sense amplifier. The first clocking signal enables the first sense amplifier to read the data on the input and complementary input lines, while the first isolating signal isolates the first sense amplifier from the input and complementary input lines. An output is then provided to the latch based upon the data read by the first sense amplifier. A second clocking signal and a second isolating signal are then input into the second sense amplifier to enable the second sense amplifier to read the data on the input and complementary input lines. The state of the latch may or may not change based upon the data read by the second sense amplifier.

Claims

1. A data sensing circuit for use with a memory array, comprising:

a latch for holding an output state;

a first CMOS dynamic sense amplifier connected to an input line and a complementary input line, and having an output connected to the latch for writing an output state thereto;

a second CMOS dynamic sense amplifier connected to the input line and complementary input line, and having an output connected to the latch for writing an output state thereto; and

a clocking circuit connected to the first and second sense amplifiers, wherein the clocking circuit generates a first clocking signal which enables the first sense amplifier to sense data on the input line and complementary input line and write the sensed data to the latch through the first sense amplifier output, and wherein the clocking circuit generates a second clocking signal, after a predetermined period after the first clocking signal, which enables the second sense amplifier to sense data on the input line and complementary input line and write the sensed data to the latch through the second sense amplifier output, and wherein the first and second clocking signals are generated during one read cycle of the memory array.

2. The circuit of claim 1, wherein the first sense amplifier is recovered before the second sense amplifier provides an output to the latch.

3. The circuit of claim 1, wherein the first and second sense amplifiers are equilibrated before the first and second clock signals are generated in preparation for a single read cycle of the memory array.

4. The circuit of claim 1, wherein the first sense amplifier is isolated from the input and complementary input line when reading the data on the input and complementary input line.

5. The circuit of claim 1, wherein the second sense amplifier is isolated from the input and complementary input line when reading the data on the input and complementary input line.

6. The circuit of claim 1, wherein the input line is a bit line in the memory array, and the complementary input line is a complementary bit line in the memory array.

7. The circuit of claim 1, wherein the latch disables the first sense amplifier output when the second sense amplifier writes an output state to the latch.

8. A method for reading data from a memory array, comprising the steps of:

applying an equilibrating signal to a first and a second CMOS dynamic sense amplifier in preparation for a single read cycle of the memory array, wherein the first and second sense amplifiers are connected to an input line and a complementary input line;

applying a first clocking signal to the first sense amplifier to enable the first sense amplifier to read the data on the input and complementary input lines;

isolating the first sense amplifier from the input and complementary input lines when applying the first clocking signal;

reading the data on the input and complementary input lines;

providing a state to a latch connected to the first and second sense amplifiers as a result of the first sense amplifier reading the data on the input and complementary input lines;

after the first clocking signal is applied, applying a second clocking signal to the second sense amplifier to enable the second sense amplifier to read the data on the input and complementary input lines;

reading the data on the input and complementary input lines; and

providing an output state to the latch as a result of the second sense amplifier reading the data on the input and complementary input lines.

9. The method of claim 8, further comprising the step of isolating the second sense amplifier from the input and complimentary input lines when applying the second clocking signal.

10. The method of claim 8, wherein the latch is constructed so that the output state of the second sense amplifier has priority over the output state of the first sense amplifier.

11. The method of claim 8, wherein the latch is constructed utilizing a second isolating signal as an input, and wherein the output state of the second sense amplifier has priority over the output state of the first sense amplifier.

12. The method of claim 8, further comprising the step of recovering the first sense amplifier before the second sense amplifier provides the state to the latch.

13. The method of claim 8, wherein said step of applying the second clock signal to the second sense amplifier occurs after a predetermined time period from the step of applying the first clocking signal to the first sense amplifier.

14. The method of claim 8, further comprising the step of:

ceasing to apply the first clocking signal to the first sense amplifier before the second clock signal is applied to the second sense amplifier.

15. The method of claim 14, wherein the first and second clock signal are pulses, and wherein the first clock signal pulse is completed before the second clock signal pulse is applied.