Memory system for loading peripherals on power up

• US 5,455,923 A
• Filed: 01/14/1993
• Issued: 10/03/1995
• Est. Priority Date: 07/30/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Cecil H. Kaplinsky
• Inventors: Kaplinsky, Cecil H.
• Primary Examiner(s): Robertson, David L.
• Assistant Examiner(s): Fenick, Sharon
• Application Number:
  US08/004,797
• Time in Patent Office: 992 Days
• Field of Search: 395/775, 395/425
• US Class Current: 711/154
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A non-volatile memory connected to state logic is provided for autoloading peripheral target devices at power-on or system reset. The memory is preloaded with commands and data. At power-on or system reset the commands are executed in sequence, transferring data to selected target devices. Data is output in bit-serial fashion on a single line. Target devices are individually selected through use of separate clock lines. Clock signals on the clock lines can be internally generated using the state logic or a target-device-supplied clock can be received under program selection. The system reset signal is intercepted and retransmitted to control target device mode. System reset polarity, enable signal polarity, data block length, clock direction, internal clock frequency, and power-saving shutdown upon completion of all transfers are all programmably selectable features.

Claims

1. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory having means for transferring its stored contents on power-up or reset of the computer system, said memory storing both commands and data simultaneously, wherein data consist of blocks of information to be transferred to said peripheral devices for initialization thereof, said memory having a byte wide input register, a byte wide output register, and an array of memory elements grouped in addressable storage bytes holding said commands and said data, and

a finite state means connected to said memory for receiving all of said commands and said data directly therefrom, wherein commands consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data to said peripheral devices, an oscillator means connected to said finite state means to produce pulses of selected length to facilitate the timing of a transfer of each data block from said memory to said specified peripheral devices, said finite state means further comprising an output means connected to a plurality of said peripheral devices for communicating pulses thereto, said finite state means further including

(a) a memory address counter means for providing a memory address to access selected commands and data from said addressable storage bytes,

(b) a data transfer length counter means for counting a selected number of said bytes of data to be output from said addressable storage bytes, and

(c) a means for receiving a plurality of strap signals on STRAP-IN lines, then carrying out a logical AND operation on a logic level associated with each of said strap signals and a different bit of a specified bit field of said accessed selected commands, then loading a resulting logical product into predetermined bit positions of said data transfer length counter means and loading zeros into remaining bit positions of said data transfer length counter means, then decrementing the loaded contents of said data transfer length counter means until said decremented contents are equal to a predetermined number, and incrementing an address in said memory address counter means each time said contents of said data transfer length counter means is being decremented.

2. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory having means for transferring its stored contents on power-up or reset of the computer system, said memory storing both commands and data simultaneously, wherein data consist of blocks of information to be transferred to said peripheral devices for initialization thereof, said memory having a byte wide input register, a byte wide output register, and an array of memory elements grouped in addressable storage bytes holding said commands and said data, and

a finite state means connected to said memory for receiving all of said commands and said data directly therefrom, wherein commands consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data to said peripheral devices, an oscillator means connected to said finite state means to produce pulses of selected length to facilitate the timing of a transfer of each data block from said memory to said specified peripheral devices, said finite state means further comprising an output means connected to a plurality of said peripheral devices for communicating pulses thereto, wherein at least one of said commands is a WAIT command, said WAIT command initiating a sequence of operations, including loading command bytes representing a number from said memory into a data transfer length counter means, then decrementing the number in said data transfer length counter means until said number is equal to a predetermined second number, then incrementing the contents of a memory address counter and fetching a next command.

3. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line, DATA_-- OUT, to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means;

said finite state means further including a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal

said finite state means further including a RESET_-- IN input line for receiving a reset input signal which initializes said finite state means when at an active signal level and which initiates a plurality of output data transfers from said memory means upon a transition from an active to an inactive signal level, and a RESET_-- OUT output line connected to all of said peripheral devices, for transmitting a substitute reset signal with an active signal level while said reset input signal is active and continuing to have an active signal level while said output data transfers are in progress.

4. An autoload memory system as set forth in claim 3 wherein a transition to an inactive signal level of said reset input signal initiates a fetch and execution of a first command block by said finite state means.

5. An autoload memory system, in a computer system, for initializing a plurality Of peripheral devices connected to said computer systems said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line, DATA_-- OUT, to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, wherein said command blocks include a bit field specifying one of the plurality of CLOCK/EN lines and a single bit designating an input/output status of said one of said CLOCK/EN lines specified by said bit field, said finite state means having means for interpreting said command blocks to perform specified functions including selecting said specified CLOCK/EN line for use by a clock signal to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means; and

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal.

6. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line, DATA_-- OUT, to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said command blocks including a bit field used to specify a clock transition direction for a selected CLOCK/EN output signal, a first direction being defined by a signal transition from a first level to a second level and a second direction being defined by a signal transition from a second level to a first level, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means; and

said finite state means further comprising a means connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal.

7. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices;

said command blocks including a field designating one of a plurality of serial data transfer protocols preprogrammed into said finite state means to facilitate an output data transfer, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means; and

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal, and said enable signal.

8. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said .peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means, wherein said command blocks include a field specifying an integer wherein said frequency divider means receives and divides a basic clock frequency of said basic clock signal by said integer to obtain said resulting clock signal; and

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and enable signal on two of said CLOCK/EN lines connected to the same said Specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal add said enable signal.

9. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means; and

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal, wherein said command blocks include a bit field designating whether an enable signal is transmitted, said enable signal remaining at a predetermined level throughout an output data transfer, and another bit field which specifies one of the plurality of CLOCK/EN lines for output of said enable signal.

10. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means; and

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal,

wherein said command blocks include a bit field redefining a function of said memory means to operate as a serial read/write memory upon completion of a power-on data transfer, said memory means being an electrically erasable memory, said bit field also redefining a function of said finite state means to include (1) serially receiving a memory address, a data block length, and a read/write command via a DATA_-- IN input line and a serial input register means, (2) interpreting and executing said read/write command using said memory address as a starting address for access to said memory means, (3) writing serially received data into said memory means during execution of a write command, (4) reading data from said memory means for serial output via a DATA_-- OUT output line during execution of a read command, (5) modifying said memory address to effect a data transfer at another memory address of said memory means, (6) comparing a data transfer length with a command block field specifying a data block length and terminating transfer of said data upon completion, and (7) remaining in a state of readiness to receive and execute additional read/write commands.

11. An autoload memory system as in claim 10 further including a guard address in said command blocks and means for comparing a received read/write memory address and for not executing the read/write command if the received address is less than the guard address.

12. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means being an electrically erasable memory, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means;

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal, and

a serial input register means connected to receive serial information via a DATA_-- IN input line for transferring its register contents to said memory means for storage or to said finite state means for interpretation and execution as a command.

13. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means; and

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal,

said command blocks including a bit field designating whether upon completion of all data transfers said autoload memory system shuts down or remains active.

14. An autoload memory system, in a computer systems, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means;

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal; and

said finite state means further including

(a) memory address counter means for providing a memory address to access commands and data from selected command and data blocks stored in said memory means,

(b) data transfer length counter means for counting a selected number of bytes of data to be output from said memory means, and

(c) means for receiving a plurality of strap signals on STRAP-IN lines, then carrying out a logical AND operation on a logic level associated with each of the strap signals and a different bit of a specified command field, then loading a resulting logical product into predetermined bit positions of the data transfer length counter means and loading zeros into remaining bit positions of the data transfer length counter means, then decrementing the loaded contents of said data transfer length counter means until the decremented contents are equal to a predetermined number, and incrementing an address in the memory address counter means each time the contents of the data transfer length counter means is being decremented.

15. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

a memory means for storage of both pre-loaded command blocks and pre-loaded data blocks simultaneously, wherein said data blocks consist of information to be transferred to said peripheral devices for initialization thereof, said memory means having means for transferring its stored contents on power-up or reset of the computer system, said memory means having an output;

an output register means having an input connected to said output of said memory means to receive said data blocks from said memory means and having a data output line DATA_-- OUT to provide said data blocks at least one bit at a time on said DATA_-- OUT line, said DATA_-- OUT line connecting in common with all of said peripheral devices allowing a data block intended for one specific peripheral device to also be received by all other peripheral devices simultaneously;

a plurality of CLOCK/EN lines connected to said plurality of peripheral devices;

a finite state means connected to said output of said memory means to receive directly from said memory means all of said command blocks, wherein said command blocks consist of bytes of information to be interpreted by said finite state means, including information designating a specified peripheral device as a destination for each data block, to facilitate transfer of said data blocks to said peripheral devices, said finite state means having means for interpreting said command blocks to perform specified functions including selecting a specific CLOCK/EN line for output of a clock signal used to transfer said data blocks on the DATA_-- OUT line;

a clock generator having oscillator means for generating a basic clock signal and frequency divider means for changing a frequency of said basic clock signal and for supplying a resulting clock signal to said finite state means;

said finite state means further comprising a means, connected to the plurality of CLOCK/EN lines, and responsive to said command block information designating a specified peripheral device, for transmitting to said specified peripheral device both said resulting clock signal and an enable signal on two of said CLOCK/EN lines connected to the same said specified peripheral device, whereby a data block intended for that specified peripheral device designated by said command block and transmitted on said DATA_-- OUT line to all of said peripheral devices is loaded only into said specified peripheral device receiving said clock signal and said enable signal, wherein at least one command block includes a WAIT command, the WAIT command initializing a sequence of operations including loading command bytes representing a number from the memory means into a data transfer length counter means of said finite state means, then decrementing the number in the data transfer counter means until the number is equal to a predetermined second number, then incrementing the contents of a memory address counter of said finite state means and fetching a next command.

16. An autoload memory system, in a computer system, for initializing a plurality of peripheral devices connected to said computer system, said autoload memory system comprising:

means for activation of the memory system at power on or system reset, the activation means including a RESET-IN line for receiving a reset signal, and a RESET-OUT line for outputting a signal which will be asserted when a signal on the RESET-IN line is asserted or when a busy control signal is asserted;

memory means being organized as a plurality of addressable locations, each addressable location storing one byte of information, the memory means having a set of memory address lines for receiving a location address, and having a set of memory output lines for outputting said byte of information stored at an addressed location, the memory means providing storage for at least one command block and at least one data block, said at least one data block consisting of bytes of data to be transferred to said peripheral devices for initialization thereof, bytes of information in said at lest one command block consisting of commands for facilitating transfer of said bytes of data to said peripheral devices;

a data output register being connected to receive a byte of data from the memory output lines, the byte of data being accepted when a load control signal is asserted, the contents of the register being output at least one bit at a time on at least one DATA_-- OUT line when a shift control signal is asserted;

memory address counter means having outputs connected to provide address signals on the memory address lines, the memory address counter means being responsive to an initialize control signal whereby an address stored in said memory address counter means is preset to an initial address, and to an increment control signal which causes the memory address counter means to increment the address stored therein from a present address to a next address;

data transfer length counter means for counting the number of bits of data output by the data output register, the data transfer length counter means being organized into a plurality of byte wide sections, each byte wide section being connected to receive a byte of information in a command block from the memory output lines and being responsive to a specific byteload control signal for loading said byte of information into that section, the plurality of byte wide sections being organized to function together as a counter whose loaded bytes of information together represent an initial count, which is decremented from a present count to a next count when a decrement control signal is asserted, the data transfer length counter means providing a done signal which is asserted when the decremented count is equal to a predetermined count;

command register means connected to receive commands from the memory output lines when a fetch control signal is asserted, predetermined subfields of the command register means being connected to a decoding means for decoding command bits of the subfields to produce a plurality of command decode signals, the command register means being responsive to a preset control signal for presetting the contents of the command register means to a predetermined code;

a clock generator for providing a clock signal, the clock generator having a divider for increasing a duty cycle length and pulse width of a data transfer clock signal which is output on one of a plurality of CLOCK lines connected to said plurality peripheral devices;

a sequential state machine connected to receive the reset signal, the command decode signals, the done signal, and the clock signal and to produce therefrom all the control signals in proper sequences to fetch and execute the commands and to output each data block to a target peripheral device.

17. The autoload memory system of claim 16 further including a plurality of programmable I/O pads respectively connected to said DATA_-- OUT line and said CLOCK line, a command including a subfield being decodable to select a programmable I/O pad as an input line or an output line.

18. The autoload memory system of claim 16 wherein the clock generator further includes programmable means for receiving an external data transfer clock signal on a CLOCK_-- IN line and providing this clock signal for use in serially outputting data.

19. The autoload memory system of claim 16 further including means for receiving a control input signal on a CONTROL_-- IN line, an asserted level of the control input signal causes said sequential state machine to temporarily suspend operation until said control input signal returns to a non-asserted level.

20. The autoload memory system of claim 19 wherein the asserted level of the control input signal disables said DATA_-- OUT line and said CLOCK line.

21. The autoload memory system of claim 19 wherein a non-asserted level of the control signal causes the sequential state machine to suspend operation, and an asserted level of the control signal causes the sequential state machine to resume operation.

22. The autoload memory system of claim 16 further including means for receiving a plurality of strap signals on STRAP-IN lines, then carrying out a logical AND operation on a logic level associated with each of the strap signals and a different bit of a specified command field, then loading a resulting logical product into predetermined bit positions of the data transfer length counter means and loading zeros into remaining bit positions of the data transfer length counter means, then decrementing the loaded contents of said data transfer length counter means until the decremented contents are equal to a predetermined number, and incrementing an address in the memory address counter means each time the contents of the data transfer length counter means is being decremented.

23. The autoload memory system of claim 16 wherein at least one command block includes a WAIT command, the WAIT command initiating a sequence of operations including loading command bytes representing a number from the memory means into the data transfer length counter means, then decrementing the number in the data transfer length counter means until the the decremented number is equal to a predetermined second number, then incrementing the contents of the memory address counter means and fetching a next command.