Method for testing the electrical parameters of inputs and outputs of integrated circuits without direct physical contact

• US 5,457,381 A
• Filed: 10/02/1992
• Issued: 10/10/1995
• Est. Priority Date: 09/30/1991
• Status: Expired due to Fees

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Farwell, William D.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/955,579
• Time in Patent Office: 1,103 Days
• Field of Search: 324/158.1, 324/73.1, 324/763-537, 437/8, 371/15.1, 371/22.5, 371/22.6, 371/22.3, 371/22.1, 377/70, 364/481, 364/480
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

Test circuitry implemented in an integrated circuit having a plurality of I/O circuits for testing of the electrical parameters of the I/O circuits without probing the contact pads associated therewith. The test circuitry includes a test drive bus, a test drive pad connected to the test drive bus, a test observe bus, a test observe pad connected to said test observe bus. Associated with each I/O circuit are a test drive transmission gate connected between the associated I/O pad and the test drive bus, and a test observe transmission gate connected between the associated I/O pad and the test observe bus. The transmission gates for each pad are controlled in parallel via a scan control register, and are connected by separate conductive traces to the I/O pad. If an I/O includes an input buffer, the input to the input buffer is connected to the I/O pad via the separate conductive trace to the test drive transmission gate; and if an I/O has an output driver, the output to the output driver is connected to the I/O pad via the separate conductive trace for the test observe transmission gate.

Claims

1. In a circuit having a plurality of I/O circuits wherein each input/output (I/O) circuit comprises an input circuit having an input buffer, an output circuit having an output driver, each I/O circuit having an associated pad, test circuitry comprising:

a test observe bus;

a test observe pad connected to said test observe bus;

a test drive bus;

a test drive pad connected to said test drive bus;

first selection means associated with each I/O circuit for controllably conductively connecting the associated I/O pad to said test observe bus;

a test drive conductive trace connected between said first selection means and the associated I/O pad, said test drive conductive trace being further connected an input buffer if the I/O circuit includes an input buffer;

second selection means associated with each I/O circuit for controllably conductively connecting the associated I/O pad to said test drive bus;

a test observe conductive trace connected between said first selection means and the associated I/O pad, test observe conductive trace being further to an output driver if the I/O circuit includes an output driver;

whereby the I/O pad of a selected I/O circuit can be conductively connected to said test drive bus and to said test observe bus, such that electrical parameters of the I/O circuits can be tested without physically probing the associated I/O pads.

2. The test circuitry of claim 1 wherein said first selection means comprises a test drive transmission gate conductively connected between said test drive conductive trace and said test drive bus, and wherein said second selection means comprises an observe transmission gate connected between said test observe conductive trace and said test observe bus.

3. The test circuitry of claim 2 wherein the test drive transmission gate and the observe transmission gate for an I/O are controlled in parallel via a scan register.

4. In a integrated circuit having a plurality of bidirectional input/outputs (I/O) circuits each having an input buffer, and an associated I/O contact pad, test circuitry comprising:

a respective test observe conductive trace for each bidirectional I/O circuit for connecting the output of the three-state driver to the associated I/O pad;

a respective test drive conductive trace for each bidirectional I/O for connecting the input of the input buffer to the associated I/O pad;

a test observe bus;

a test observe pad connected to said test observe bus;

a test drive bus;

a test drive pad connected to said test observe bus; and

first selection means for each bidirectional I/O circuit for controllably conductively connecting said test observe conductive trace to said test observe bus; and

second selection means for each bidirectional I/O circuit for controllably conductively connecting said test drive conductive trace to said test drive bus;

whereby the I/O pad of a selected bidirectional I/O circuit can be conductively connected to said test drive bus and to said test observe bus, such that electrical parameters of the I/Os can be tested without physically probing the I/O pads.

5. The test circuitry of claim 4 wherein said

wherein said first selection means comprises a test drive transmission gate conductively connected between the associated bidirectional I/O pad and said test drive bus;

and

wherein said second selection means comprises an observe transmission gate conductively connected between the associated bidirectional I/O pad and said test observe bus.

6. The test circuitry of the claim 5 wherein the test drive transmission gate and the observe transmission gate for a bidirectional I/O circuit are controlled in parallel via test control logic.

7. The test circuitry of claim 6 wherein said test control logic includes a scan register.

8. In an integrated circuit having a plurality of input circuits each having an input buffer and an associated I/O contact pad, test circuitry comprising:

a respective test observe conductive trace for each input circuit having one end connected to the associated I/O pad;

a respective test drive conductive trace for each input circuit for connecting the input of the input buffer to the associated I/O pad;

a test observe bus;

a test observe pad connected to said test observe bus;

a test drive bus;

a test drive pad connected to said test observe bus; and

a test observe transmission gate for each input circuit for controllably conductively connecting said test observe conductive trace to said test observe bus; and

a test drive transmission gate for each input circuit for controllably conductively connecting said test drive conductive trace to said test drive bus;

whereby the I/O pad of a selected input circuit can be conductively connected to said test drive bus and to said test observe bus, such that electrical parameters of the input circuits can be tested without physically probing the I/O pads.

9. In an integrated circuit having a plurality of output circuits each having an output driver and an associated I/O contact pad, test circuitry comprising:

a respective test observe conductive trace for each output circuit for connecting the output of the output driver to the associated I/O pad;

a respective test drive conductive trace for each input circuit having one end connected to the associated I/O pad;

a test observe bus;

a test observe pad connected to said test observe bus;

a test drive bus;

a test drive pad connected to said test observe bus; and

a test observe transmission gate for each input circuit for controllably conductively connecting said test observe conductive trace to said test observe bus; and

a test drive transmission date for each input circuit for controllably conductively connecting said test drive conductive trace to said test drive bus;

whereby the I/O pad of a selected output circuit can be conductively connected to said test drive bus and to said test observe bus, such that electrical parameters of the output circuits can be tested without physically probing the I/O pads.