Load short-circuit detection using AWH-bridge driving circuit and an exclusive-OR gate

• US 5,457,391 A
• Filed: 08/23/1993
• Issued: 10/10/1995
• Est. Priority Date: 09/03/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Shimizu, Toshifumi, Mori, Kazuhiro, Iwanami, Yumiko
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): TOBIN, C
• Application Number:
  US08/110,368
• Time in Patent Office: 778 Days
• Field of Search: 324/210-212, 324/522-523, 324/546, 324/706, 324/713, 360/31, 361/86, 361/168.1, 361/169.1, 361/187
• US Class Current: 324/546
• CPC Class Codes: G01R 31/42 AC power supplies
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults

Abstract

A load short-circuit state detection circuit has a driver including X and Y terminals between which an inductive load is connected and receiving drive signals. The detection circuit further includes a first transistor whose base is connected to the X terminal and whose collector is supplied with a voltage, a second transistor whose base is connected to the Y terminal and whose collector is also supplied with a voltage, a first constant current circuit connected to an emitter of the first transistor through a first resistor and a second constant current circuit connected to an emitter of the second transistor through a second resistor. A comparator is provided for comparing a voltage of a node between the first resistor and the first constant current circuit with a voltage of a node between the second resistor and the second constant current circuit. An exclusive OR gate circuit receives one of the drive signals supplied to the driver and an output signal of the comparator and executes an exclusive OR operation on these signals. The comparator is capable of detecting a potential difference between the two input signals.

Claims

1. A load short-circuit detection circuit, comprising:

an H-bridge-type load driving circuit provided with first through fourth input terminals to which first through fourth drive signals are supplied for driving an inductive load with an alternating current, and X and Y terminals between which the inductive load is connected;

a first transistor a base of which is connected to the X terminal and a collector of which is supplied with a first voltage;

a first resistor one terminal of which is connected to an emitter of the first transistor;

a first constant current source connected to the other terminal of the first resistor;

a second transistor a base of which is connected to the Y terminal and a collector of which is supplied with a second voltage;

a second resistor one terminal of which is connected to an emitter of the second transistor;

a second constant current source connected to the other terminal of the second resistor;

a comparing circuit for receiving a voltage of a node between the first resistor and the first constant current source and a voltage of a node between the second resistor and a second constant current source, comparing the received voltages and outputting a signal with a level corresponding to a comparison result;

an exclusive OR gate circuit, coupled to one of said first to fourth terminals and to said comparing circuit, for receiving one of the first through fourth drive signals and the signal outputted from the comparing circuit and executing an exclusive OR operation on said one of the drive signals and said outputted signal.

2. The circuit according to claim 1, wherein the H-bridge type load driving circuit comprises:

a third transistor a base of which is connected to the first input terminal and a collector of which is applied with a predetermined voltage;

a fourth transistor a base of which is connected to the second input terminal and a collector of which is connected to the emitter of the third transistor and the X terminal;

a fifth transistor a base of which is connected to the third input terminal and a collector of which is applied with a predetermined voltage;

a sixth transistor a base of which is connected to the fourth input terminal, a collector of which is connected to an emitter of the fifth transistor and the Y terminal, and an emitter of which is connected to an emitter of the fourth transistor; and

a constant current circuit connected to the emitters of the fourth and sixth transistors;

and wherein the first and fourth drive signals having substantially same phase are supplied to the first and fourth input terminals and the second and third drive signals having substantially same phase but opposite to the phase of the first and fourth drive signals are supplied to the second and third input terminals.

3. The circuit according to claim 1, wherein:

the first voltage is identical with the second voltage;

a resistor value of the load is RH;

values of the first and second resistors are R1 and R2, respectively;

a value of a current flowing into the first and second transistors is I;

the first transistor is substantially identical with the second transistor;

a value of a current flowing into the load when the load is in a normal condition is IW;

the comparing circuit is capable of detecting a potential difference PV of two input signals; and

the RH, R1, R2, I, IW, and PV satisfy the following two equations;

space="preserve" listing-type="equation">I·

(R2-R1)-IW·

RH<

-PV

space="preserve" listing-type="equation">I·

(R2-R1)<

-PV.

4. A load short-circuit detection circuit, comprising:

a driving circuit of H-bridge type, having X and Y terminals between which an inductive load is connected, for receiving at least one driving signal and supplying an alternating current to the inductive load in response to said at least one driving signal;

an amplifying circuit, coupled to the driving circuit, for amplifying voltages at the X and Y terminals;

a comparing circuit connected to the amplifying circuit, for comparing the amplified voltages of the X and Y terminals with each other and outputting a signal with a level corresponding to a comparison result; and

an exclusive OR gate circuit, connected to the driving circuit and the comparing circuit, for executing an exclusive OR operation on said at least one driving signal and the signal outputted from the comparing circuit.