Semiconductor array having built-in test circuit for wafer level testing

• US 5,457,400 A
• Filed: 07/23/1993
• Issued: 10/10/1995
• Est. Priority Date: 04/10/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahmad, Aftab, Weber, Larren G., Green, Robert S.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US08/096,643
• Time in Patent Office: 809 Days
• Field of Search: 324/158 F, 324/158 R, 324/73.1, 324/763, 324/754, 324/158.1, 324/765, 371/22.1, 371/22.5, 371/22.6, 371/25.1
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A test circuit is provided for an integrated circuit device, whereby an oscillator is provided on-chip and is activated by a test circuit. The test circuit provides an ability to test the devices while still on the wafer and facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. The oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the DUT at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.

Claims

1. In an integrated circuit device formed on a semiconductor wafer and having functional circuitry, a test circuit for testing the functional circuitry, said test circuit comprising:

a) an oscillator circuit formed on said integrated circuit device for providing a periodic output;

b) the oscillator circuit including circuitry for varying a period of the periodic output in order to vary a test parameter;

c) circuitry for receiving the periodic output from the oscillator circuit and providing a timing signal to the functional circuitry of the integrated circuit device as a device under test DUT, the timing signal having a period which is proportional to the periodic output, said timing signal controlling test sequences during said testing of the functional circuitry, such that a variation in the test parameter as a result of varying the period of the periodic output permits the response of the functional circuitry of the DUT at different operating speeds to be determined;

d) a scanning circuit for determining outputs of the functional circuitry; and

e) a response circuit responsive to the scanning circuitry for providing an error signal during said testing; and

f) a nonvolatile memory responsive to the error signal for retaining an indication of test results.

2. The test circuit of claim 1, further comprising:

the oscillator circuit including a ring oscillator.

3. The test circuit of claim 1, further comprising:

a) the oscillator circuit including a ring oscillator; and

b) the circuitry for varying the period being a frequency divider which receives an oscillator output signal from the ring oscillator and provides a signal which is a fraction of the ring oscillator'"'"'s output signal, the frequency divider further being adjustable in order to adjust the period of the periodic output.

4. The test circuit of claim 1, further comprising:

a) the DUT being testable while in wafer form prior to separation of the integrated circuit device from other integrated circuit devices on said wafer; and

b) a grid containing a plurality of conductive traces on the wafer, the conductive traces extending from external connection points to each DUT so that power applied to the conductive traces enable testing of the DUTs in said wafer form.

5. The test circuit of claim 1, further comprising:

a) the DUT being testable while in wafer form prior to separation of the integrated circuit device from other integrated circuit devices on said wafer;

b) a grid containing a plurality of conductive traces on the wafer, the conductive traces extending from external connection points to each DUT so that power applied to the conductive traces enable testing of the DUTs in said wafer form;

c) the grid being deposited on the wafer in such a manner that a grid may be removed subsequent to testing, whereupon the integrated circuit devices may be operated in a normal manner with said grid removed, thereby permitting the integrated circuit devices to be operated without enabling the test circuitry; and

d) said removal of the grid being accomplished by removing a metal mask layer from the wafer.

6. The test circuit of claim 4, further comprising:

a) the plurality of conductive traces on the wafer including a power supply grid and a common grid;

b) one of said power supply and common grids further providing a test enable signal to each DUT.

7. The test circuit of claim 4, further comprising:

a) the plurality of conductive traces on the wafer including a power supply grid and a common grid;

b) the plurality of conductive traces on the wafer further including a grid which provides each DUT on the wafer with a unique address.

8. In an integrated circuit device formed on a semiconductor wafer and having a functional circuit array, a test circuit for testing the functional circuit array, said test circuit comprising:

a) a burnin circuit formed on the integrated circuit device, in electrical communication with the functional circuit array and which permits the functional circuit array to be selectively operated in a normal operating mode by which the functional circuit array may be addressed through external connections and a burnin code, and in which the burnin circuit causes the integrated circuit device to cycle through predetermined sequences for addressing at least a substantial portion of the functional circuit array;

b) an oscillator circuit formed on the integrated circuit device in electrical communication with the burnin circuit for providing a periodic output;

c) the oscillator circuit including circuitry for varying the period of the periodic output of the oscillator circuit;

d) circuitry in electrical communication with the oscillator circuit for receiving the periodic output from the oscillator circuit and providing a timing signal to the functional circuit array, the timing signal having a period which is proportional to the periodic output, such that a variation in a test parameter with a variation in the period of the periodic output permits the response of the functional circuit array at different operating speeds to be determined;

e) scanning circuitry for determining outputs of the functional circuit array;

f) a response circuit responsive to the scanning circuitry for providing an error signal; and

g) a nonvolatile memory responsive to said error signal for retaining an indication of test results.

9. The test circuit of claim 8, further comprising:

a) a data comparison circuit, the data comparison circuit comparing the periodic output with data received from the semiconductor circuit device and generating an error signal when the data comparison circuit detects a mismatch between the periodic output with data received from the semiconductor circuit device; and

b) a latch circuit, the latch circuit being responsive to the error signal and the sequential indication signal, thereby providing an indication of sequential event during which the error was detected.

10. The test circuit of claim 8, further comprising:

the oscillator circuit including a ring oscillator.

11. The test circuit of claim 8, further comprising:

a) the oscillator circuit including a ring oscillator; and

b) the circuitry for varying the period being a frequency divider which receives an oscillator output signal from the ring oscillator and provides a signal which is a fraction of the ring oscillator'"'"'s output signal, the frequency divider further being adjustable in order to adjust the period of the periodic output.

12. The test circuit of claim 8, further comprising:

a) the oscillator circuit including a ring oscillator; and

b) the circuitry for varying the period having at least four frequency adjustment circuits in order to adjust the period of the periodic output.

13. The test circuit of claim 8, further comprising:

a) the functional circuit array being testable while in the form of a wafer which contains a plurality of similar devices, each of said plurality being a functional circuit array; and

b) a grid containing a plurality of conductive traces on the wafer, the conductive traces extending from external connection points to each functional circuit array so that power applied to the conductive traces enable testing of the functional circuit arrays on the wafer.

14. The test circuit of claim 8, further comprising:

a) the functional circuit array being testable while in the form of a wafer which contains a plurality of similar devices, each of said plurality being a functional circuit array;

b) a grid containing a plurality of conductive traces on the wafer, the conductive traces extending from external connection points to each functional circuit array so that power applied to the conductive traces enable testing of the functional circuit arrays on the wafer; and

c) the grid being deposited on the wafer in such a manner that a grid may be removed subsequent to testing, whereupon the integrated circuit devices may be operated in a normal manner with said grid removed, thereby permitting the integrated circuit devices to be operated without enabling the burnin circuitry.

15. The test circuit of claim 14, further comprising:

a) the plurality of conductive traces on the wafer including a power supply grid and a common grid;

b) one of said power supply and common grids further providing a test enable signal to each functional circuit array.

16. The test circuit of claim 14, further comprising:

a) the plurality of conductive traces on the wafer including a power supply grid and a common grid;

b) the plurality of conductive traces on the wafer further including a grid which provides each functional circuit array on the wafer with a unique address.

17. The test circuit of claim 14, further comprising:

said removal of the grid being accomplished by removing a metal mask layer from the wafer.

18. The test circuit of claim 14, further comprising:

said removal of the grid being accomplished by removing a metal mask layer from the wafer by the use of a mechanical planarization process.