Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals

• US 5,457,412 A
• Filed: 11/10/1993
• Issued: 10/10/1995
• Est. Priority Date: 11/17/1992
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hiramoto, Toshiro, Ohayashi, Masayuki, Tamba, Nobuo, Saito, Kayoko, Odaka, Masanori
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/149,935
• Time in Patent Office: 699 Days
• Field of Search: 307/475, 307/443, 307/455, 307/446, 307/463, 365/230.06, 326/64, 326/66, 326/126, 326/110, 326/105, 326/108, 326/17-18
• US Class Current: 326/66
• CPC Class Codes: H03K 19/017527 with at least one differential stage

Abstract

A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.

Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

Claims

1. A semiconductor integrated circuit device comprising:

a first circuit which includes;

a first transistor which has a first base supplied with a first input signal having a first voltage range between high and low voltage levels of said first input signal, a first emitter and a first collector, wherein the first input signal is an ECL level signal;

a second transistor which has a second emitter coupled to the first emitter, a second collector and a second base supplied with a reference voltage corresponding to the first input signal;

a third transistor which has a third base coupled to the second collector, a third emitter and a third collector, and which outputs a first output signal in response to a collector potential of the second collector, wherein the first output signal has a second voltage range between high and low voltage levels of said first output signal which is wider than the first voltage range of the first input signal;

a first ground terminal which is supplied with a ground potential and which is coupled to the first, second and third collectors; and

a first power supply terminal which is supplied with a first operating voltage and which is coupled to the first, second and third emitters,

wherein a level of the first operating voltage is set to prevent operation of the first and second transistors in their saturation regions,

a second circuit which decodes the first output signal and which outputs a second output signal having a third voltage range between high and low voltage levels of said second output signal which is wider than the second voltage range of said first output signal, wherein the second circuit is coupled between a second ground terminal supplied with the ground potential and a second power supply terminal supplied with a second operating voltage of a higher level than the first operating voltage; and

a memory array which includes;

a plurality of memory cells each including complementary MOSFETs; and

a plurality of word lines which are coupled to the memory cells, and in which a word line is selectively selected in response to the second output signal, and wherein each of the memory cells is coupled between a third ground terminal supplied with the ground potential and a third power supply terminal supplied with a third operating voltage having an absolute value thereof being larger than an absolute value of a low level voltage of the second output signal.

2. A semiconductor integrated circuit device comprising:

a first circuit which includes;

a first transistor which has a first base supplied with a first input signal having a first voltage range between high and low voltage levels of said first input signal, a first emitter and a first collector, wherein the first input signal is an ECL level signal;

a second transistor which has a second emitter coupled to the first emitter, a second collector and a second base supplied with a reference voltage corresponding to the first input signal;

a third transistor which has a third base coupled to the second collector, a third emitter and a third collector, and which outputs a first output signal in response to a collector potential of the second collector, wherein the first output signal has a second voltage range between high and low voltage levels of said first output signal which is wider than the first voltage range;

a first ground terminal which is supplied with a ground potential and which is coupled to the first, second and third collectors; and

a first power supply terminal which is supplied with a first operating voltage and which is coupled to the first, second and third emitters,

wherein a level of the first operating voltage is set to prevent operation of the first and second transistors in their saturation regions,

a second circuit which includes;

a fourth transistor which has a fourth base supplied with a second input signal having a voltage range between high and low voltage levels of the second input signal which is substantially the same as said first voltage range, a fourth emitter and a fourth collector, wherein the second input signal is an ECL level signal,

a fifth transistor which has a fifth emitter coupled to the fourth emitter, a fifth collector and a fifth base supplied with a reference voltage corresponding to the second input signal;

a sixth transistor which has a sixth base coupled to the fifth collector, a sixth emitter and a sixth collector, and which outputs a second output signal in response to a collector potential of the fifth collector, wherein the second output signal has a voltage range between high and low voltage levels of said second output signal which is substantially the same as said second voltage range and which is wider than the first voltage range;

a second ground terminal which is supplied with the ground potential and which is coupled to the fourth, fifth and sixth collectors; and

a second power supply terminal which is supplied with the first operating voltage and which is coupled to the fourth, fifth and sixth emitters,

wherein a level of the first operating voltage is so set to prevent operation of the fourth and fifth transistors in their saturation regions,

a third circuit which decodes the first and second output signals and which outputs a third output signal having a third voltage range between high and low voltage levels of said third output signal, which third voltage range is wider than the second voltage range, wherein the third circuit is coupled between a third ground terminal supplied with the ground potential and a third power supply terminal supplied with a second operating voltage of a higher level than the first operating voltage; and

a memory array which includes;

a plurality of memory cells including complementary MOSFETs, and

a plurality of word lines which are coupled to the memory cells, and in which a word line is selectively selected in response to the third output signal, and wherein each of the memory cells is coupled between a fourth ground terminal supplied with the ground potential and a fourth power supply terminal supplied with a third operating voltage having an absolute value thereof being larger than an absolute value of a low level voltage of the third output signal.

3. A semiconductor integrated circuit device according to claim 2, further comprising a diode element which is coupled between the decoder circuit and the second power supply terminal in order to supply the second power supply terminal with the first operating voltage instead of supplying it with the second operating voltage.

4. A semiconductor integrated circuit device according to claim 3, wherein the second power supply terminal is coupled to the first power supply terminal.

5. A semiconductor integrated circuit device according to claim 2, wherein a voltage difference between the absolute value of second operating voltage and that of the third operating voltage is lower than a threshold voltage of a MOSFET of at least one of the complimentary MOSFETs forming said memory cells.

6. A semiconductor integrated circuit device according to claim 5, further comprising a first load resistor coupled between the first ground terminal and the collector of the first transistor, and a second load resistor coupled between the first ground terminal and the collector of the second transistor.

7. A semiconductor integrated circuit device according to claim 6, further comprising a first constant current source circuit coupled between the first power supply terminal and the emitters of the first and second transistors, and a second constant current source circuit coupled between the first power supply terminal and the emitter of the third transistor.

8. A semiconductor integrated circuit device according to claim 7, further comprising a seventh transistor coupled to the first transistor in parallel, which has a seventh base supplied with a third input signal having voltage range between high and low voltage levels of said third input signal which is substantially the same as said first voltage range, where the third input signal is an ECL level signal.

9. In a semiconductor integrated circuit device having an input buffer circuit, a decoder circuit which receives output signals from the input buffer circuit and a memory array coupled to the decoder circuit, wherein the input buffer circuit includes:

a differential circuit which receives a first input signal having a first voltage range between high and low voltage levels of said first input signal and a reference voltage corresponding to the first input signal, and which has a first transistor and a second transistor coupled in a differential form, wherein the first input signal is an ECL level signal;

an emitter-follower circuit which has a third transistor outputting a first output signal, as one of the output signals of the input buffer circuit, in response to an output signal outputted from the differential circuit, wherein the first output signal has a second voltage range between high and low voltage levels of said first output signal which is wider than the first voltage range;

a first ground terminal which is supplied with a ground potential and which is coupled to the differential circuit and the emitter-follower circuit; and

a first power supply terminal which is supplied with a first operating voltage and which is coupled to the differential circuit and the emitter-follower circuit,

wherein a level of the first operating voltage is set to prevent operation of the first and second transistors in their saturation regions,

wherein the decoder circuit decodes the output signals from the input buffer circuit and outputs a second output signal having a third voltage range between high and low voltage levels of said second output signal which is wider than the second voltage range, and wherein the decoder circuit is coupled between a second ground terminal supplied with the ground potential and a second power supply terminal supplied with a second operating voltage of a higher level than the first operating voltage; and

wherein the memory array includes;

a plurality of memory cells including complementary MOSFETs; and

a plurality of word lines which are coupled to the memory cells, and in which a word line is selectively selected in response to the second output signal, and wherein each of the memory cells is coupled between a third ground terminal supplied with the ground potential and a third power supply terminal supplied with a third operating voltage having an absolute value thereof being larger than an absolute value of a low level voltage of the second output signal.