Software controlled adaptive delta modulator

• US 5,457,714 A
• Filed: 10/13/1992
• Issued: 10/10/1995
• Est. Priority Date: 08/21/1991
• Status: Expired due to Fees

• Current Assignee: WavePhore, Inc.
• Original Assignee: WavePhore, Inc.
• Inventors: Smith, Michael J., Bethel, Michael D., Sowell, Michael A., Engel, Melvyn
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Webster, Bryan
• Application Number:
  US07/959,981
• Time in Patent Office: 1,092 Days
• Field of Search: 375/27, 375/28, 375/29, 375/24, 341/143, 341/166
• US Class Current: 375/247
• CPC Class Codes: H03M 3/022 with adaptable step size, e.g. adaptive delta modulation [ADM]

Abstract

A delta modulator automatically adjusting the slewing rate is disclosed. In the absence of a transition in the output data of a delta modulator, a parameter used for the integrator of the delta modulator is increased. When the comparator of the modulator indicates that the feedback signal of the modulator has overshot the input signal, the parameter is decreased or reversed until the two signals are approximately equal as signalled by a 50% duty cycle.

Claims

1. A processor in one of a delta modulator and receiver in response to a serial bit stream representative of an analog signal, the processor comprising:

an arithmetic logic unit performing arithmetic and logic functions in response to a program;

a plurality of memory areas for storing data produced by the arithmetic logic during performance of the program;

a program memory storing a program for selecting the data to be used, and the arithmetic and logic functions to be performed, wherein one of the stored datum is a first quantity proportional to the analog signal, the program memory including a program for causing the arithmetic logic unit to generate a delta modulated serial bit stream

and the program memory including the steps of incrementing or decrementing a value based upon the serial data stream;

selectively altering the data in response to a transition in the bit stream;

accumulating the selectively altered data to generate the first quantity; and

providing the first quantity to the digital to analog converter; and

a digital to analog converter coupled to receive the quantity.

2. The processor of claim 1, wherein the program memory further includes a memory look-up table such that in response to different data streams, different portions of the memory look-up table are used for selecting the functions to be performed by the arithmetic logic unit.

3. The processor of claim 1, further including:

a comparator receiving an analog input signal at a first input, and a signal proportional to the output of the digital to analog converter as the second input, the serial data stream being the output of the comparator.

4. The processor of claim 1, the program further including the steps of:

periodically sampling the first quantity and accumulating those samples for a predetermined interval;

determining if the magnitude of the accumulation of those periodic samples exceeds a predetermined magnitude; and

decreasing from time to time the first magnitude of the first quantity during the subsequent interval.

5. The processor of claim 4, wherein the predetermined interval is longer than the period of an audible sound.

6. The processor of claim 4, wherein the frequency of decreasing the magnitude of the first quantity is one-third of the frequency of accumulating the selectively altered data.

7. The processor of claim 1, wherein the processor further includes a means for monitoring the output to the digital to analog processor and for resetting the processor to an initial state if no activity is detected at the output after a predetermined period of time.

8. A processing circuit responsive to delta modulation data, the improvement comprising:

an input pattern detector to detect different sequences of the delta modulation data;

a first bidirectional accumulator accumulating a quantity in different directions in response to that input pattern detector;

a transformer responsive to the pattern detector for selectively outputting an altered first quantity in response to only certain detected input patterns and otherwise outputting the first quantity;

a second bidirectional accumulator accumulating the output of the transformer; and

a digital to analog converter responsive to the accumulated output of the transformer.

9. The processing circuit of claim 8 further including a comparator for comparing the output of the converter and an input analog signal, the output of the comparator providing the delta modulation data.

10. The processing circuit of claim 8 wherein the processing circuit includes:

an arithmetic logic unit and a plurality of memory means; and

wherein each of the input pattern detector, the first accumulator, the transformer and the second accumulator each comprise at least one memory means and the arithmetic logic unit is used sequentially in combination with the separate memory means to detect the input pattern, accumulate the quantities and transform the quantity.

11. The processing circuit of claim 8, wherein the processing circuit further includes:

a third accumulator to accumulate the output of the second accumulator;

a comparator to determine if the magnitude of the third accumulator has exceeded a predetermined limit; and

means responsive to the comparator for altering the magnitude of the second accumulator if the comparator indicates that the predetermined limit has been exceeded.

12. In a delta modulator for converting an analog signal into a digital output signal, the output of the modulator providing sequential samples of a comparison between the analog input signal and an integration of the output signal, wherein the integration occurs in response to a controlled signal, the improvement comprising:

an accumulator that accumulates a count;

means for controlling the magnitude of the controlled signal in differing proportions to the count; and

means for increasing the count in response to the absence of a change in the output and to otherwise decreasing the count to a minimum, the means for increasing and decreasing the count comprises means for increasing the count in response to a first predetermined sequence and for decreasing the magnitude of the controllable signal in response to a different sequence.

13. A delta modulator/demodulator processor for selectively receiving an analog input signal and a digital input delta modulated signal and producing in response to the analog input signal an output digital delta modulated bit stream and producing an analog output signal in response to the digital input signal, the processor comprising:

a control means for selecting whether the processor will delta modulate the analog input signal or demodulate the digital input data, wherein the control means includes a voice detector and selects between modulating and demodulating based upon the output of that detector;

a feedback signal generator providing a feedback signal as an analog output when delta demodulation is selected;

a comparator that compares the analog input signal to the feedback signal; and

a sampler responsive to the comparator that provides the digital output signal in response to the delta demodulator when delta modulation is selected.

14. The processor of claim 13, wherein the control means is responsive to a push to talk switch.

15. The processor of claim 13, wherein the control means includes a voice detector and selects between modulating and demodulating based upon the output of that detector.

16. A processor for providing an output delta modulation representation of an analog input signal and an analog output representation of an input delta modulation signal, the delta processor comprising:

an arithmetic logic unit performing arithmetic and logic functions in response to a program;

a plurality of memory areas for storing data produced by the arithmetic logic unit during performance of the program;

a program memory storing a program for selecting the data to be used, and the arithmetic and logic functions to be performed, wherein one of the stored datum is a first parameter proportional to the analog input signal and a second stored datum comprising an accumulation based upon the delta modulation signal

a digital to analog converter responsive to one of the first and second stored datum, the analog output of the processor being the output of the converter;

a comparator responsive to the analog input signal and the output of the converter, wherein the digital output of the processor comprises a sampling of the comparator output by the processor

and wherein the processor has a control input, the processor providing the analog output only in response to a first condition at the control input and providing the digital output only in response to a second condition at the input.

17. In a delta modulator receiver susceptible to DC offsets and for transforming a delta modulated data stream into an analog output signal, the delta modulator comprising:

an alterable accumulator accumulating a parameter based upon the sampled output and an offset signal;

a feedback signal generator generating the feedback signal based upon the accumulated output; and

a filter responsive to the accumulator to generate the offset signal to thereby remove DC offsets and wherein

the receiver includes an arithmetic processing unit and alterable memory and wherein the accumulator includes a memory within a processor holding the accumulated parameter and the filter includes a second memory location holding a second accumulated parameter.

18. A method for processing delta modulation data, the improvement comprising:

detecting different sequences of the delta modulation data;

accumulating a quantity in different directions in response to that input pattern detector;

providing as a second quantity either a transformed first quantity in response to only certain detected input patterns and otherwise a quantity equal to the first quantity;

accumulating the second quantity; and

converting the accumulated second quantity into an analog voltage having a magnitude that is proportional to the accumulated quantity.

19. The method of claim 18, wherein the method further comprises:

comparing the analog voltage with an input signal, and providing the delta modulation data based upon the comparison.

20. The method of claim 18, wherein the method further comprises:

accumulating the accumulated second quantity to provide a third quantity;

determining if the third quantity exceeds a predetermined limit; and

altering the magnitude of the second accumulated quantity if the predetermined limit has been exceeded.