Adaptive configurable gate array
First Claim
1. A master slice, comprising:
- a semiconductor wafer;
a sea of gates formed in and covering substantially the entire surface of said semiconductor wafer, said sea of gates defining a configurable gate array having a continuum of transistors from which at least one application specific integrated circuit (ASIC) chip is capable of being formed by selectively connecting together a subset of the continuum of transistors and cutting through unconnected transistors to separate the ASIC chip from the wafer, said configurable gate array being free of predefined boundaries along which the semiconductor wafer must be cut; and
a plurality of islands in said sea of gates and separate from the transistor continuum for aiding in forming the ASIC chip prior to its separation from the wafer.
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Abstract
A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer.
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Citations
18 Claims
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1. A master slice, comprising:
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a semiconductor wafer; a sea of gates formed in and covering substantially the entire surface of said semiconductor wafer, said sea of gates defining a configurable gate array having a continuum of transistors from which at least one application specific integrated circuit (ASIC) chip is capable of being formed by selectively connecting together a subset of the continuum of transistors and cutting through unconnected transistors to separate the ASIC chip from the wafer, said configurable gate array being free of predefined boundaries along which the semiconductor wafer must be cut; and a plurality of islands in said sea of gates and separate from the transistor continuum for aiding in forming the ASIC chip prior to its separation from the wafer. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A master slice, comprising:
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a semiconductor wafer; said semiconductor wafer having a surface of predetermined surface area on which to form transistors; a continuum of uniformly spaced transistors formed in and covering at least a major portion of said predetermined surface area of said semiconductor wafer with said transistors being of substantially identical N-channel and P-channel MOSFET transistors, said transistors defining a configurable gate array from which at least one application specific integrated circuit (ASIC) chip is capable of being formed, said configurable gate array being free of predefined boundaries along which the semiconductor wafer must be cut; and a plurality of islands in said surface area surrounded by said plurality of transistors, said islands being void of said transistors and occupying a minor portion of said predetermined surface area to define a locale for receiving devices other than said transistors.
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8. A master slice configurable gate array for use in the producing of at least two semiconductor chips, each of said semiconductor chips having an area which includes at a base layer level only a plurality of transistors, comprising:
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a semiconductor wafer; said semiconductor wafer having a predetermined surface area on which to form said configurable gate array; said configurable gate array being formed from a continuum of transistors formed in and substantially covering at least a major portion of said predetermined surface area of said semiconductor wafer and being free of predefined boundaries therebetween; said transistors being of substantially identical N-channel and P-channel type MOSFET transistors; and said continuum of transistors defining a region of said predetermined surface area within which said semiconductor chips are formed entirely of said transistors by selectively connecting together a subset of the continuum of transistors and cutting through unconnected transistors to separate the ASIC chip from the wafer. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A configurable gate array comprising:
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a semiconductor wafer having a major surface; a continuum of transistors that are uniformly spaced in rows and columns throughout substantially the entire major surface of the wafer, said transistors being free of boundaries therebetween, said wafer containing a sufficient number of transistors to form a variety of application specific integrated circuit (ASIC) chips of different sizes from the same wafer size, the ASIC chips ranging from an ASIC chip of a first size using a first number of transistors to a second ASIC chip of a second size utilizing substantially all of the continuum of transistors in the wafer; and saw lane channels overlying selected portions of the transistors in the semiconductor wafer, said saw lane channels defining lanes for cutting the wafer through portions of the underlying transistors to define a desired ASIC chip from the wafer.
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Specification