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BiCMOS circuit for translation of ECL logic levels to MOS logic levels

  • US 5,459,412 A
  • Filed: 07/01/1993
  • Issued: 10/17/1995
  • Est. Priority Date: 07/01/1993
  • Status: Expired due to Term
First Claim
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1. A translator circuit for translating from a first logic-level range to a second logic-level range, said translator circuit comprising:

  • (a) an input stage having a first input transistor for receiving a first input signal and a second input transistor for receiving a second input signal which is the complement of said first input signal, wherein said first input transistor and said second input transistor are coupled to a high-potential power rail;

    (b) an output stage having a first output transistor coupled to a second output transistor and a third output transistor coupled to a fourth output transistor, wherein said output stage is a CMOS output stage and said first output transistor and said third output transistors are PMOS transistors, and said second output transistor and said fourth output transistor are NMOS transistors, wherein said first output transistor is coupled to said high-potential power rail and to said first input transistor, wherein said second output transistor is coupled to a low-potential power rail and to said fourth output transistor, wherein said third output transistor is coupled to said high-potential power rail and to said second input transistor and wherein said fourth output transistor is coupled to said low-potential power rail; and

    (c) a reference stage including;

    (i) a first reference transistor, wherein said first reference transistor is a PMOS transistor, wherein a source node of said first reference transistor is coupled to said high-potential power rail, wherein a gate node of said first reference transistor is coupled to a drain node of said first reference transistor and wherein a drain node of said first reference transistor is coupled to a low-potential power rail through a bipolar regulating transistor of a first current regulator; and

    (ii) a second reference transistor wherein said second reference transistor is a bipolar transistor having a collector node coupled to said high potential power rail, a base node coupled to said drain node of said first reference transistor, and an emitter node coupled to a gate node of said first output transistor and a gate node of said third output transistor.

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