Video images decoder architecture for implementing a 40 MS processing algorithm in high definition television
First Claim
1. A video image decoder for processing the 40-ms mode on high-resolution TV sets, of a kind handling TV signals, comprising:
- a video signal demultiplexer receiving as an input fields J and L, wherein J and L are successive odd fields of a series of fields;
two processing blocks for separately handling the signals from each of the fields and each comprising,a video image format converter,a local memory connected to an output of the format converter, andat least one median filter and one systolic filter in cascade connection after said memory for restoring, by interpolation, signal samples related to successive lines of the video image so as to provide an output of the processing block; and
a summing node for adding together the outputs from each processing block so as to obtain a time mean between restored samples of the fields J and L.
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Abstract
A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (J,L), which comprises a video signal demultiplexer receiving the transmission channels (J,L); and respective processing blocks for separately handling the signals from each of the channels (J,L). Each processing block includes a video image format converter, a local memory connected to an output of the converter, and at least one median filter and one systolic filter cascade connected after the memory for restoring, by interpolation, signal samples related to successive lines of the video image. A summing node adds the outputs from each processing block so as to obtain a time mean between restored samples of the channels (J,L). This architecture drastically reduces the number of memories required for processing the restored algorithm, as well as reducing overall silicon area requirements for the system. Accordingly, the whole 40-millisecond processing portion may be integrated into a single chip.
45 Citations
28 Claims
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1. A video image decoder for processing the 40-ms mode on high-resolution TV sets, of a kind handling TV signals, comprising:
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a video signal demultiplexer receiving as an input fields J and L, wherein J and L are successive odd fields of a series of fields; two processing blocks for separately handling the signals from each of the fields and each comprising, a video image format converter, a local memory connected to an output of the format converter, and at least one median filter and one systolic filter in cascade connection after said memory for restoring, by interpolation, signal samples related to successive lines of the video image so as to provide an output of the processing block; and a summing node for adding together the outputs from each processing block so as to obtain a time mean between restored samples of the fields J and L. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A video image decoder for processing the 40-ms mode of a TV signal of HDMAC format, comprising:
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a demultiplexer for demultiplexing said TV signals into an J field and a L field, wherein the J field and the L field are successive odd fields; a first and second processing block, the first processing block receiving the J field and the second processing block receiving the L field, each processing block including an image format converter for receiving a respective field and providing formatted output therefrom; memory means for receiving and storing the formatted output, median filter means for concurrently providing a first plurality of median values based upon a received second plurality of inputs which are selected from the memory means in accordance with a working window of interpolation, and systolic filtering means for producing a restored output of the respective field, said systolic filtering means receiving the first plurality of median values and receiving a third plurality of inputs selected from the memory means in accordance with the working window, the systolic filtering means including means for concurrently interpolating missing horizontal samples of at least two lines of the respective field and including means for interpolating missing vertical samples of the respective field in accordance with a motion vector of the TV signal; and
output means for producing a time mean of the restored outputs, said output means outputting the restored outputs and the time mean. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A video image decoder for processing the 40-ms mode of a TV signals of HDMAC format, comprising:
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a demultiplexer for demultiplexing said TV signals into an J field and a L field, wherein the J field and the L field are successive odd fields; a first and second processing block, the first processing block receiving the J field and the second processing block receiving the L field, each processing block including an image format converter for receiving a respective field and providing formatted output therefrom memory for receiving and storing the formatted output, median filter for concurrently providing a first plurality of median values based upon a received second plurality of inputs which are selected from the memory in accordance with a working window of interpolation, and systolic filter for producing a restored output of the respective field, the systolic filter receiving the first plurality of median values and receiving a third plurality of inputs selected from the memory in accordance with the working window, the systolic filter including a horizontal interpolater for concurrently interpolating missing horizontal samples of at least two lines of the respective field and including a vertical interpolater for interpolating missing vertical samples of the respective field in accordance with a motion vector of the TV signal; and
output node for producing a time mean of the restored outputs, said output node outputting the restored outputs and the time mean. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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Specification