Active matrix liquid crystal display with supplemental capacitor line which overlaps signal line

• US 5,459,596 A
• Filed: 03/29/1993
• Issued: 10/17/1995
• Est. Priority Date: 09/14/1992
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ueda, Tomomasa, Akiyama, Masahiko, Sugahara, Atsushi, Shibusawa, Makoto, Ikeda, Mitsushi, Tsuji, Yoshiko, Toeda, Hisao
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US08/038,989
• Time in Patent Office: 932 Days
• Field of Search: 359/59, 359/54, 359/84, 359/87, 359/67, 257/59, 257/60
• US Class Current: 349/39
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136218 Shield electrodes

Abstract

An active matrix type liquid crystal display device having a plurality of scan lines, a plurality of signal lines intersected with the plurality of scan lines, the plurality of scan lines being insulated from the plurality of signal lines, a thin film transistor element having a gate portion and a drain portion and disposed at each intersection of the plurality of scan lines and the plurality of signal lines, the gate portion being connected to a scan line at the intersection, the drain portion being connected to a signal line at the intersection, an array substrate formed in the intersection and having a pixel electrode, the pixel electrode being electrically connected to the source portion of the thin film transistor element, an opposite substrate having an opposite electrode opposed to the array substrate, a liquid crystal layer disposed between the array substrate and the opposite substrate, and a shield electrode disposed on the array substrate, the shield electrode being overlaid through an insulation layer with at least part of the pixel electrode and with at least part of at least either the scan line or signal line.

Claims

1. An active matrix type liquid crystal display device, comprising:

an array substrate, said array substrate including;

a first substrate,

a plurality of scan lines and a plurality of signal lines formed on said first substrate,

said plurality of signal lines intersecting said plurality of scan lines and insulated from said plurality of scan lines,

a thin film transistor element having a gate portion, drain portion and source portion, and disposed at each intersection of said plurality of scan lines and signal lines, said gate portion being connected to said scan line, and said drain portion being electrically connected to said signal line,

a separate pixel electrode electrically connected to said source portion of each said thin film transistor element,

a shield electrode layer extending in lapped relation with at least one side of said pixel electrode and in lapped relation with a portion of a signal line, the intersecting ones of said scan and signal lines being in proximate relation to adjacent sides of said pixel electrode, said shield electrode layer extending in lapped relation with at least one side of a plurality of said pixel electrodes, and

an insulation layer disposed between said shield electrode layer and said pixel electrode and said portion of said signal line;

a second substrate having an opposite electrode and disposed in opposed relation with said array substrate; and

a liquid crystal layer disposed between said array and second substrates.

2. The active matrix type liquid crystal display device as set forth in claim 1, wherein said shield electrode layer extends in lapped relation with a portion of said signal line, said portion of said signal line being coextensive with the side of said pixel electrode in proximate relation thereto.

3. The active matrix type liquid crystal display device as set forth in claim 1, wherein said shield electrode layer and a gate electrode layer of said thin film transistor element are portions of a single layer.

4. An active matrix type liquid crystal display device, comprising:

an array substrate, said array substrate including;

a first substrate,

a plurality of scan lines and a plurality of signal lines formed on said first substrate,

said plurality of signal lines intersecting said plurality of scan lines and insulated from said plurality of scan lines,

a thin film transistor element having a gate portion, drain portion and source portion, and disposed at each intersection of said plurality of scan lines and signal lines, said gate portion being connected to said scan line, and said drain portion being electrically connected to said signal line,

a separate pixel electrode electrically connected to said source portion of each said thin film transistor element,

a shield electrode layer extending in lapped relation with three sides of said pixel electrode and with a portion of one of intersecting ones of said scan lines and signal lines, the intersecting ones of said scan and signal lines being in proximate relation to adjacent sides of said pixel electrode, said shield electrode layer extending in lapped relation with at least one side of a plurality of said pixel electrodes, a fourth side of said pixel electrode in non-lapped relation with said shield electrode layer being electrically connected to said source portion of said thin film transistor, and

an insulation layer disposed between said shield electrode layer and said pixel electrode and said portion of said one of said scan and signal lines;

a second substrate having an opposite electrode and disposed in opposed relation with said array substrate; and

a liquid crystal layer disposed between said array and second substrates.

5. An active matrix type liquid crystal display device, comprising:

an array substrate, said array substrate including;

a first substrate,

a plurality of scan lines and a plurality of signal lines formed on said first substrate,

said plurality of signal lines intersecting said plurality of scan lines and insulated from said plurality of scan lines,

a thin film transistor element having a gate portion, drain portion and source portion, and disposed at each intersection of said plurality of scan lines and signal lines, said gate portion being connected to said scan line, and said drain portion being electrically connected to said signal line,

a separate pixel electrode electrically connected to said source portion of each said thin film transistor element,

a shield electrode layer extending in lapped relation with at least one side of said pixel electrode and with a portion of one of intersecting ones of said scan lines and signal lines, the intersecting ones of said scan and signal lines being in proximate relation to adjacent sides of said pixel electrode, said shield electrode layer extending in lapped relation with at least one side of a plurality of said pixel electrodes,

an insulation layer disposed between said shield electrode layer and said pixel electrode and said portion of said one of said scan and signal lines, and

a storage capacitor formed at a location where said shield electrode is lapped with the side of said pixel electrode;

a second substrate having an opposite electrode and disposed in opposed relation with said array substrate; and

a liquid crystal layer disposed between said array and second substrates,

wherein a width W_cs of said shield electrode layer and said pixel electrode in lapped relation, is given by the following equation;

6. 7 W_cs^opt <

W_cs <

2W_cs^opt

where W_cs^opt is an optimum lap width having a minimum deviation of a pixel voltage shift,

where

space="preserve" listing-type="equation">W.sub.cs.sup.opt =(L.sub.g ·

L.sub.cs ·

C.sub.si -2β

·

C.sub.1c-max) / (2L.sub.cs ·

C.sub.si)

where

L_g is the width of the gate electrode;

L _cs is the length of the center line of the portion where the pixel electrode and the shield electrode which forms a storage capacitor is overlapped;

C _si is the capacitance of the storage capacitor per unit si area;

C_1c--max is the maximum capacitance of one pixel of the LCD;

C_1c--min is the minimum capacitance of one pixel of the LCD; and

β

is a constant (where β

=(C_1c-max +C_1c--min) /2C_1c-max).

7. An active matrix type liquid crystal display device, comprising:

an array substrate, said array substrate including;

a first substrate,

a plurality of scan lines and a plurality of signal lines formed on said first substrate,

said plurality of signal lines intersecting said plurality of scan lines and insulated from said plurality of scan lines,

a thin film transistor element having a gate portion, drain portion and source portion, and disposed at each intersection of said plurality of scan lines and signal lines, said gate portion being connected to said scan line, and said drain portion being electrically connected to said signal line,

a separate pixel electrode electrically connected to said source portion of each said thin film transistor element,

a shield electrode layer extending in lapped relation with at least one side of said pixel electrode and with a portion of one of intersecting ones of said scan lines and signal lines, the intersecting ones of said scan and signal lines being in proximate relation to adjacent sides of said pixel electrode, said shield electrode layer extending in lapped relation with at least one side of a plurality of said pixel electrodes,

wherein said shield electrode layer and said first substrate are held at a common electric potential; and

an insulation layer disposed between said shield electrode layer and said pixel electrode and said portion of said one of said scan and signal lines;

a second substrate having an opposite electrode and disposed in opposed relation with said array substrate; and

a liquid crystal layer disposed between said array and second substrates.