Integrated semiconductor memory with redundancy arrangement

• US 5,459,690 A
• Filed: 08/17/1992
• Issued: 10/17/1995
• Est. Priority Date: 04/16/1992
• Status: Expired due to Term

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Stecker, Johann, Rieger, Johann
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): ZARABIAN, AMIR
• Application Number:
  US07/920,315
• Time in Patent Office: 1,156 Days
• Field of Search: 365/200, 365/230.03, 365/230.06, 365/195
• US Class Current: 365/200
• CPC Class Codes: G11C 29/781 combined in a redundant decoder
• CPC Class Codes: G11C 29/806 by reducing size of decoders
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

An integrated semiconductor memory has a block decoder BKDEC having block selection signals BKS and a plurality of main memory area block units BK which can be individually activated. The main memory area block units BK contain memory locations which can be selected via word and bit lines NWL, NBL, NBL and redundancy memory locations RMC, which can be selected via redundancy word lines RWL. The main memory area block units BK contain programmable redundancy block decoders RBK, which in conjunction with redundancy word line decoders RWDEC enable the selection of redundancy word lines RWL. If a redundancy word line RWL is to be selected, it is exclusively that main memory area block unit BK in which the redundancy word line RWL that is to be selected is contained that is activated. In this case, activation which is otherwise usual is suppressed via an appropriate block selection signal BKS. It is rendered possible in this way that the redundancy word line RWL that is to be selected together with its redundancy memory locations RMC can be arranged in a different main memory area block unit BK from the memory locations to be replaced together with their normal word lines NWL, but also in an (any) other main memory area block unit BK. It is possible in this way to increase the yield in the production of integrated semiconductor memories.

Claims

1. An integrated semiconductor memory with redundancy arrangement, which has the following characteristics:

normal memory cells (NMC), which are disposed in a plurality of memory field block units (BK) that are individually activatable via associated activation units (ACT);

the memory field block units (BK) are activatable via their activation units (ACT) by means of block selection signals (BKS), and the block selection signals (BKS) can be generated by block decoders (BKDEC) from a first part (BKAD) of word line address signals (WLAD) that can be applied to the semiconductor memory;

the normal memory cells (NMC) are addressable per memory field block unit (BK) via normal word lines (NWL) and normal bit lines (NBL, NBL*);

normal word line decoders (NWDEC) for selecting a normal word line (NWL) in a memory field block unit (BK) as a function of a second part (WL2AD) of the word line address signals (WLAD), under the control of the block selection signal (BKS) associated with the applicable memory field block unit (BK);

bit line decoders (BDEC) for selecting a normal bit line (NBL, NBL*) as a function of bit line address signals (BLAD) that can be applied to the semiconductor memory;

redundant memory cells (RMC) in the memory field block units (BK) along redundant word lines (RWL);

programmable redundant word line decoders (RWDEC) in the memory field block units (BK) for selection of a redundant word line (RWL) as a function of the second part (WL2AD) of the word line address signals (WLAD), in the case in which on the basis of a programming that has been carried out of a redundant word line decoder (RWDEC), memory cells along normal word lines (NWL) are to be functionally replaced via redundant memory cells (RMC) that are addressable via an applicable redundant word line (RWL), characterized by

at least one programmable redundant block decoder (RBK) for selection of the redundant word line decoders (RWDEC), both in cases in which a redundant word line (RWL) to be selected, having replacement redundant memory cells (RMC), is located in the same memory field block unit (BK) as the normal line (NWL) having the memory cells to be replaced, and in cases in which a redundant word line (RWL) to be selected, having replacement redundant memory cells (RMC), is disposed in an arbitrary different memory field block unit (BK) from the normal word line (NWL) having the memory cells to be replaced.

2. The integrated semiconductor memory of claim 1, characterized in that the at least one programmable redundant block decoder (RBK) is connected on an input side to the first part (BKAD) of the word line address signals (WLAD), and that in the programmed state it generates redundant block selection signals (RBKS) for triggering the redundant word line decoders (RWDEC) in the memory field block units (BK).

3. The integrated semiconductor memory of claim 1, characterized in that

when more than one programmable redundant block decoder (RBK) is present, the programmable redundant block decoders (RBK) are disposed in each memory field block unit (BK) with redundant word lines (RWL).

4. The integrated semiconductor memory of claim 1, characterized in that

when more than one programmable redundant block decoder (RBK) is present, the programmable redundant block decoders (RBK) are disposed in the memory field block units (BK);

that the programmable redundant block decoders (RBK) are connected on the input side with all the block selection signals (BKS); and

that the programmable block decoder (RBK) of an applicable memory field block unit (BK) is programmable such that in the programmed state, on its output side it activates a redundant block selection signal (RBKS) for triggering the redundant word line decoders (RWDEC) of that memory field block unit (BK) also whenever the memory cells to be replaced are located in a different one from the applicable memory field block unit (BK).

5. The integrated semiconductor memory of claim 1, characterized in that an applicable one of the redundant word line decoder (RWDEC) triggered by the redundant block decoder (RBK) generates an inhibit signal (INHIB), which is common to all the memory field block units (BK) and has an activated state, for inhibiting all the activation units (ACT) of the semiconductor in the case in which the applicable redundant word line decoder (RWDEC), on the basis of the second part (WL2AD) of the word line address signals (WLAD), selects one of the redundant word lines (RWL), while the inhibit signal (INHIB) otherwise has an inactive state.

6. The integrated semiconductor memory claim 1, characterized in that each of the memory field block units (BK) contains an activation signal (0ACT),

which has an activated state if on the one hand one of the redundant word line decoders (RWDEC) in the applicable memory field block unit (BK) is selected by the applicable redundant block selection signal (RBKS), and if on the other hand this selected redundant word line decoder (RWDEC), on the basis of the applied second part (WL2AD) of the word line address signals (WLAD), selects a redundant word line (RWL), and

which otherwise has an inactive state, in which the activation signal (0ACT) in its activated state takes on the function of the block selection signal (BKS) that is responsible for the applicable memory field block unit (BK), so that the applicable memory field block unit (BK) is activated, by means of its activation unit (ACT), despite the activated state of the inhibit signal (INHIB).

7. The integrated semiconductor memory of claim 1, characterized in that the programmable redundant block decoders (RBK) are part of the redundant word line decoders (RWDEC).

8. The integrated semiconductor memory of claim 5, characterized in that by means of the inhibit signal (INHIB) in the activated state, a deactivation of the block decoder (BKDEC) is effected, instead of a deactivation of the activation units (ACT).

9. The integrated semiconductor memory of claim 5, characterized in that by means of the inhibit signal (INHIB) in the inactivated state, a deactivation of the block decoder (BKDEC) takes place in addition to the deactivation of the activation units (ACT).

10. The integrated semiconductor memory claim 1, characterized in that it has a programmable delay circuit (DLY), which in the programmed state delays the activation of an activated block selection signal (BKS) of an applicable memory field block unit (BK) by a predetermined period of time (t2), while in the non-programmed state, no delay takes place.

11. The integrated semiconductor memory of claim 10, characterized in that the delay circuit (DLY), in the non-programmed state, prevents an activation of the inhibit signal (INHIB).

12. The integrated semiconductor memory of claim 10, characterized in that the delayed activation takes place in the activation unit (ACT) of the applicable memory field block unit (BK).

13. The integrated semiconductor memory of claim 11, characterized in that the prevention of the activation of the inhibit signal (INHIB) takes place in the redundant word line decoders (RWDEC).

14. The integrated semiconductor memory of claim 10, characterized in that the programmability is dictated by a programmable element (F).

15. The integrated semiconductor memory of claim 10, characterized in that the delay circuit (DLY) is programmed only in the case in which, on the basis of programming undertaken, any one of the redundant block decoders (RBK) and any one of the redundant word line decoders (RWDEC) is programmed.

16. The integrated semiconductor memory of claim 10, characterized in that the delay circuit (DLY) is programmed only in the case in which, on the basis of programming undertaken of at least one redundant word line decoder (RWDEC), along with the associated redundant block decoder (RBK), at least one of the redundant word line (RWL) with replacement redundant memory cells (RMC) is disposed in a different memory field block unit (BK) from a corresponding normal word line (NWL) having the memory cells that are to be replaced.