Apparatus and method for digital circuit testing

• US 5,459,738 A
• Filed: 01/26/1994
• Issued: 10/17/1995
• Est. Priority Date: 01/26/1994
• Status: Expired due to Fees

• Current Assignee: Hiromichi Watari
• Original Assignee: Hiromichi Watari
• Inventors: Watari, Hiromichi
• Primary Examiner(s): Cosimano, Edward R.
• Application Number:
  US08/187,638
• Time in Patent Office: 629 Days
• Field of Search: 324/73.1, 324/765, 364/579, 364/580, 371/22.1, 371/25.1, 371/27
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Abstract

An apparatus and method for digital circuit testing in which latches store a single command for each assigned node in a circuit to be tested. Buffers are used to drive the nodes of the circuit being tested in accordance with the drive commands. The outputs from the circuit being tested are selectively applied to at least one comparator. A multiplexor reduces the number of comparators required for accessing the all pertinent nodes of the digital circuit being tested.

Claims

1. A method for in-circuit testing comprising the steps of:

(a) providing a plurality of latches each connected to an input of one buffer of a plurality of buffers;

(b) writing commands into selected ones of said plurality of latches;

(c) said buffers driving selected input nodes within a digital circuit responsive to commands in said plurality of latches, said input nodes serving as inputs to the circuit being tested;

(d) making an electrical connection between an output node of the circuit being tested and a comparator for comparing the output from the output node to a threshold; and

(e) reading the output of the comparator.

2. The method of claim 1 further comprising repeating steps d and e for a plurality of different output nodes.

3. The method of claim 1 wherein at least one of the input nodes also serves as an output of a circuit.

4. A digital circuit tester comprising:

a plurality of latches, each said latch containing a single command for an assigned node on a circuit to be tested;

a plurality of drivers, each of said drivers connected to one of said latches for immediately receiving the single command contained in said one of said latches for producing a signal, responsive to the single command, at logic levels corresponding to the logic levels of the circuit to be tested and wherein each of said drivers comprises a plurality of buffers connected in parallel so as to produce a drive signal with sufficient current to drive an input of the circuit to be tested and an output of a circuit connected to the circuit to be tested; and

means for comparing outputs from the nodes of the circuit to be tested with threshold levels.

5. The circuit tester of claim 4 wherein said plurality of drivers comprise CMOS drivers for generating signals at CMOS logic levels.

6. The circuit tester of claim 4 wherein said plurality of drivers comprise ECL drivers for generating signals at ECL logic levels.

7. The circuit tester of claim 4 further comprising means for interfacing with a computer processor so that said computer processor can write commands into said plurality of latches and read outputs of said means for comparing.

8. The circuit tester of claim 7 wherein said means for interfacing comprises an electrical connector for insertion into a motherboard of a computer.

9. A digital circuit tester comprising:

means for storing commands each of a plurality of assigned nodes on a circuit to be tested;

a plurality of buffers, each of said buffers connected to receive one of the commands contained in said storing means for driving a signal, responsive to the one command, at logic levels corresponding to the logic levels of the circuit to be tested; and

means for comparing outputs from the nodes of the circuit to be tested with threshold levels.

10. The circuit tester of claim 9 wherein each of said buffers comprises a plurality of buffers connected in parallel so as to produce a drive signal with sufficient current to drive an input of the circuit to be tested and an output of a circuit connected to the circuit to be tested.

11. The circuit tester of claim 9 further comprising means for interfacing with a computer processor so that said computer processor can write commands into said storing means and read outputs of said comparing means.

12. The circuit tester of claim 11 wherein said means for interfacing comprises an electrical connector for insertion into a motherboard of a computer.

13. A digital circuit tester comprising:

means for externally driving selected nodes of a digital circuit in accordance with a predefined test;

multiplexor means having a number of inputs for connection to each node of a circuit to be tested and a plurality of outputs, wherein the number of outputs is smaller than the number of inputs; and

a plurality of comparators, each comparator connected to one of said plurality of outputs and at least one threshold, each comparator having a comparator output for giving a result of comparing the one of said plurality of outputs connected thereto with the at least one threshold.

14. The circuit tester of claim 13 further comprising a first resistance connected between each of said plurality of outputs of said multiplexor means and a supply voltage and a second resistance connected between each of said plurality of outputs of said multiplexor means and ground, said first and second resistances having resistance values such that when the one of said plurality of outputs is a high impedance a voltage in between a high and low threshold is applied to the comparator connected to said one of said plurality of outputs.

15. The circuit tester of claim 13 wherein said means for externally driving comprises a plurality of drivers each comprised of a plurality of buffers connected in parallel so as to produce a drive signal with sufficient current to drive an input of the circuit to be tested and an output of a circuit connected to the circuit to be tested.

16. The circuit tester of claim 13 further comprising an interface to a processor so that said processor controls which inputs of said multiplexor means are connected to the plurality of outputs and so that said processor can read the outputs out from said comparators.

17. The circuit tester of claim 16 wherein said interface comprises an electrical connector for insertion into a motherboard of a computer.

18. A digital circuit tester comprising:

a plurality of latches, each said latch containing a single command for an assigned node on a circuit to be tested;

a plurality of buffers, each of said buffers connected to at least one of said latches, for driving a signal on the assigned node of a circuit to be tested responsive to the at least one of said latches;

multiplexor means having a number of inputs for connection to each node of a circuit to be tested and at least one output, wherein the number of outputs is smaller than the number of inputs; and

a comparator connected to each of said at least one outputs and at least one threshold, each comparator having a comparator output for giving a result of comparing the at least one output connected thereto with the at least one threshold.

19. The digital circuit tester of claim 18 further comprising an interface to a processor so that said processor controls which inputs of said multiplexor means are connected to the at least one output and so that said processor can read the outputs from said comparator.

20. The digital circuit tester of claim 19 wherein said interface comprises an electrical connector for insertion into a motherboard of a computer.