Phase comparator for biphase coded signal including preamble with code violation
First Claim
Patent Images
1. A method of comparing phase of first and second signals, wherein the first signal is composed of periodic frames each comprising a preamble and a data interval, said method comprising:
- (a) producing an output signal according to the phase relationship between the first and second signals; and
(b) disabling step (a) during the preamble of the first signal.
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Abstract
Phase of first and second signals is compared by producing an output signal in the event of a predetermined phase relationship between the first and second signals and clearing the output signal at a predetermined phase during the cycle of the second signal regardless of the state of the first signal.
29 Citations
19 Claims
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1. A method of comparing phase of first and second signals, wherein the first signal is composed of periodic frames each comprising a preamble and a data interval, said method comprising:
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(a) producing an output signal according to the phase relationship between the first and second signals; and (b) disabling step (a) during the preamble of the first signal. - View Dependent Claims (2, 3, 4)
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5. A method of phase comparison comprising the steps of:
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receiving a first periodic signal of a first frequency, a second periodic signal of a second frequency closely matching the first frequency, and a mask signal having an enable state and a disable state; processing the second signal to produce a control signal having a reset state and a non-reset state and a frequency equal to said second frequency; if the mask signal is in the enable state, producing a first output set signal upon receiving a clocking event of the first signal and a second output set signal upon receiving a clocking event of the second signal; clearing the first and second output set signals in response to coincidence of said first and second output set signals; and clearing at least one of said first and second output set signals when the control signal is in the reset state.
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6. A phase comparison apparatus for comparing phase of a first periodic signal of a first frequency and a second periodic signal of a second frequency that closely matches the first frequency, said phase comparison apparatus comprising:
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a processing means for generating a periodic control signal in response to the second signal, wherein the frequency of the periodic control signal is equal to that of the second signal and the periodic control signal has a reset state and a non-reset state; and a phase comparator means connected to receive the first and second signals, a mask signal having an enable state and a disable state, and the control signal, and the phase comparator means being operative to produce an output signal according to the phase relationship between the first and second signals when the control signal is in its non-reset state and the mask signal is in the enable state and to modify the output signal to a predetermined state when the control signal enters its reset state. - View Dependent Claims (7, 8, 9)
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10. A phase comparison apparatus comprising:
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a phase comparator means for receiving a first periodic signal having a first frequency, a second periodic signal having a second frequency closely matching the first frequency, a control signal having a reset state and a non-reset state and a frequency equal to the second frequency, a clear signal having a logical true state and a logical false state, and a mask signal having an enable state and a disable state, and said phase comparator means being operative, if the mask signal is in the enable state, to produce a first output set signal upon receiving a first clocking event from one of said first and second signals, to produce a second output set signal of opposite polarity with respect to the first output set signal upon receiving a second clocking event from the other of said first and second signals, to clear the first and second output set signals in response to the clear signal being in the logical true state, and to clear at least one of said first and second output signals when the control signal is in the reset state; a coincidence means for receiving the first and second output set signal, and generating the clear signal in the logical true state in response to coincidence of the first and second output set signals and otherwise generating the clear signal in the logical false state; and a processing means for generating said second periodic signal and said control signal in response to said first and second output set signals.
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11. A method of processing a data signal composed of periodic frames each comprising a preamble and a data interval, said method comprising:
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(a) generating an extracted clock signal in response to the data signal, the frequency content of the clock signal being different during the preamble than during the data interval; (b) producing an output signal in the event of a predetermined phase relationship between the extracted clock signal and a second signal; (c) modifying the output signal at a predetermined phase during the cycle of the second signal regardless of the state of the extracted clock signal; and (d) disabling step (b) during the preamble. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A logic circuit comprising:
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a first D flip-flop having a D input, a clock input, a reset input, and an output, a second D flip-flop having a D input, a clock input, a reset input, and an output, an AND means having two inputs connected to the two outputs respectively of the first and second flip-flops and also having an output, the AND means asserting a logic 1 output in the event that the first and second flip-flops are both in a set state and otherwise asserting a logic 0 output, and an OR means having a first input connected to the output of the AND means, an output connected to the reset input of the first flip-flop, and also having a second input, whereby the first flip-flop is reset in the event that the two flip-flops are both in the set state or in the event that the OR means receives a logic 1 at its second input regardless of the whether the two flip-flops are both in the set state. - View Dependent Claims (19)
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Specification