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Method and arrangement for transmitting digital signals

  • US 5,459,782 A
  • Filed: 07/19/1993
  • Issued: 10/17/1995
  • Est. Priority Date: 01/17/1991
  • Status: Expired due to Fees
First Claim
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1. An arrangement for transmitting at least one incoming digital signal via a data channel having a constant clock rate, whereby data rates of a matching step are matched by positive-zero-negative stuffing in that, on reaching a predetermined upper or lower phase separation, additional stuffing processes are produced, comprising:

  • a memory into which an incoming digital signal is written using a write clock and from which reading out takes place using a read clock,a system controller connected to said memory for controlling an outgoing digital signal and the stuffing processes, anda threshold value decision device which initiates a stuffing process in the event of an upper stepped decision threshold being exceeded or a lower decision threshold being undershot, said threshold value decision device having an upper decision threshold for a phase separation of less than one unit interval and ≧

    0, which runs in a stepped manner and changes with each of N pulse frames of a stuffing superframe, and having a lower decision threshold, which proceeds uniformly therewith,means for determining phase deviations of less than one unit interval which initiate a stuffing process when a decision threshold is upwardly or downwardly transgressed,said system controller including;

    a frame generator which forms the pulse frame;

    a frame number counter connected to an output of said frame generator to count the pulse frames; and

    ,a control logic circuit connected to receive control logic circuit time criteria from the frame generator and from the frame number counter, and the control logic circuit produces a control signal which corresponds to a pulse, which is allocated to each and every pulse frame of a stuffing superframe, at different testing times, which pulse stores a difference value which indicates the occupancy level of the memory.

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