Method and arrangement for transmitting digital signals

• US 5,459,782 A
• Filed: 07/19/1993
• Issued: 10/17/1995
• Est. Priority Date: 01/17/1991
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Volejnik, Wilhelm
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/094,051
• Time in Patent Office: 820 Days
• Field of Search: 375/112, 375/118, 375/120, 375/121, 375/371, 375/376, 375/372, 375/377, 370/102, 370/84
• US Class Current: 375/372
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

During the transmission of digital signals which are interlaced in a multiplex signal, plesiochronic clock frequencies are also matched by means of positive-zero-negative stuffing. In this case, the time intervals of the phase changes can be large in comparison with the time constant of a phase low-pass filter which is formed by a phase-locked loop at the receiving end, which results in a jitter of approximately 1 UI. This jitter can be reduced if additional stuffing processes are inserted in pairs, in such a manner that an additional positive stuffing process (PST) is followed by such a negative stuffing process (NST) or, overall, vice versa, and if the time intervals within the pairs and/or between the pairs are selected in such a manner that the mean value of the phase difference between an incoming digital signal at the transmission end and an outgoing digital signal at the transmission end, which is contained in the multiplex signal, averaged over a specific time duration, remains approximately constant.

Claims

1. An arrangement for transmitting at least one incoming digital signal via a data channel having a constant clock rate, whereby data rates of a matching step are matched by positive-zero-negative stuffing in that, on reaching a predetermined upper or lower phase separation, additional stuffing processes are produced, comprising:

a memory into which an incoming digital signal is written using a write clock and from which reading out takes place using a read clock,

a system controller connected to said memory for controlling an outgoing digital signal and the stuffing processes, and

a threshold value decision device which initiates a stuffing process in the event of an upper stepped decision threshold being exceeded or a lower decision threshold being undershot, said threshold value decision device having an upper decision threshold for a phase separation of less than one unit interval and ≧

0, which runs in a stepped manner and changes with each of N pulse frames of a stuffing superframe, and having a lower decision threshold, which proceeds uniformly therewith,

means for determining phase deviations of less than one unit interval which initiate a stuffing process when a decision threshold is upwardly or downwardly transgressed,

said system controller including;

a frame generator which forms the pulse frame;

a frame number counter connected to an output of said frame generator to count the pulse frames; and

,

a control logic circuit connected to receive control logic circuit time criteria from the frame generator and from the frame number counter, and the control logic circuit produces a control signal which corresponds to a pulse, which is allocated to each and every pulse frame of a stuffing superframe, at different testing times, which pulse stores a difference value which indicates the occupancy level of the memory.

2. A method for transmitting at least one incoming digital signal in a data channel having a constant clock rate, comprising the steps of:

storing the incoming digital signal in a buffer memory;

matching a data rate of the incoming digital signal to the constant clock rate of the data channel by positive-zero-negative stuffing wherein a stuffing process is initiated if a phase difference between the incoming digital signal and an outgoing digital signal from said storing step reaches a decision threshold level, said decision threshold being one of an upper decision threshold and a lower decision threshold;

having a stuffing superframe which is defined between two possible stuffing processes in a same direction between successive of said positive and negative stuffing processes, having a constant number of pulse frames;

using for additional stuffing processes beyond required stuffing processes, wherein said required stuffing processes are implemented when the phase difference exceeds one unit interval, further comprises the steps of;

the upper decision threshold which runs in a stepped manner from a maximum value which is not more than one unit interval to a minimum value of not less than zero for initiating the stuffing process and

the lower decision threshold which runs in a same manner from a maximum value which is less than the minimum value of the upper decision threshold at a spacing of one unit interval for initiating an opposite other stuffing process;

reducing the decision thresholds during each period duration of the stuffing superframe step-by-step with each frame from the maximum values to the minimum values corresponding to said upper and lower decision thresholds and then setting the decision thresholds to the maximum values again at a beginning of a next superframe;

carrying out the additional stuffing processes in pairs by using smaller decision thresholds of said reducing step such that an additional positive stuffing process is followed by a negative stuffing process or such that an additional negative stuffing process is followed by a positive stuffing process;

varying time intervals during said carrying out step between said positive stuffing process and said negative stuffing process and between said negative stuffing process and a subsequent positive stuffing process as a function of the phase difference and the decision thresholds and as a result of the additional stuffing processes a mean value of the phase difference between the outgoing digital signal and the incoming digital signal is approximately constant and reaches approximately a rated value of zero;

evaluating difference values which indicate an occupancy level of a buffer memory as said decision thresholds for initiating the additional stuffing processes at different test moments, each test moment being allocated to one of the pulse frames of a stuffing superframe and one period of the pulse frames and an additional small time difference from a last test moment apart

transmitting the outgoing digital signal having a rate adjusted by stuffing.

3. A method as claimed in claim 2, further comprising the steps of:

combining, at a transmission end, a plurality of outgoing digital signals including said stuffing signals corresponding to said positive, zero, or negative stuffing signals to form a multiplex signal, and

splitting, at a receiving end, the multiplex signal into individual signals which are read out using a read clock at the receiving end, which is obtained in a phase-locked loop.

4. A method as claimed in claim 2, further comprising the step of:

selecting the stuffing superframe and the decision thresholds in such a manner that the phase difference between the outgoing digital signal and the incoming digital signal changes during the stuffing superframe less the difference between two adjacent decision threshold values.