Input/output bus architecture with parallel arbitration
First Claim
1. A bus interface for connection of a local data processing module to a tri-state bus, comprising:
- control means, coupled to the bus and the local data processing module, for detecting bus phases;
arbitration logic, coupled to a set of arbitration lines of the bus and responsive to the control means, including means for supplying a local arbitration code to a first designated subset of the set of arbitration lines and tri-stating other lines in the set of arbitration lines in a particular bus phase, means for supplying a local priority code to a second designated subset of the set of arbitration lines in the particular bus phase, and means, responsive to the local arbitration code and to other arbitration codes on the set of arbitration lines, and responsive to the local priority code and other priority codes on the set of arbitration lines, for detecting an arbitration win during the particular bus phase;
address means, coupled to a set of address lines of the bus and to the local data processing module, responsive to the control means for selectively supplying addresses to, and sampling addresses on the set of address lines in bus phases;
data means, coupled to a set of data lines of the bus and to the local data processing module, responsive to the control means for selectively supplying data to, and sampling data on the set of data lines in bus phases.
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Accused Products
Abstract
A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the interface devices supplies local arbitration codes to a particular line in the set of lines in the arbitration cycle, and detects an arbitration win during the same phase in response to the local arbitration code, and other arbitration codes driven on the set of lines during the arbitration cycle. Each module coupled to the bus also assigned a local priority code. During the arbitration cycle, both the arbitration code and the priority code are driven on respective subsets of the shared sets of lines. Assertion of the local priority code overrides normal requests for the bus. The arbitration logic on each module includes a bus request logic which has the effect of defining arbitration cycles, such that in a particular arbitration phase, a group of modules that asserts a bus request signal controls the bus request signal until all modules in the group have won arbitration.
55 Citations
25 Claims
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1. A bus interface for connection of a local data processing module to a tri-state bus, comprising:
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control means, coupled to the bus and the local data processing module, for detecting bus phases; arbitration logic, coupled to a set of arbitration lines of the bus and responsive to the control means, including means for supplying a local arbitration code to a first designated subset of the set of arbitration lines and tri-stating other lines in the set of arbitration lines in a particular bus phase, means for supplying a local priority code to a second designated subset of the set of arbitration lines in the particular bus phase, and means, responsive to the local arbitration code and to other arbitration codes on the set of arbitration lines, and responsive to the local priority code and other priority codes on the set of arbitration lines, for detecting an arbitration win during the particular bus phase; address means, coupled to a set of address lines of the bus and to the local data processing module, responsive to the control means for selectively supplying addresses to, and sampling addresses on the set of address lines in bus phases; data means, coupled to a set of data lines of the bus and to the local data processing module, responsive to the control means for selectively supplying data to, and sampling data on the set of data lines in bus phases. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A bus interface for connection of a local data processing module to a tri-state bus, comprising:
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control means, coupled to the bus and the local data processing module, for detecting arbitration phases, address phases and data phases for transfers on the bus; arbitration logic, coupled to a set of arbitration lines of the bus and responsive to the control means, which arbitrates for transfers during arbitration phases, including means for supplying a local arbitration code to a first designated subset of the set of arbitration lines and tri-stating the other lines in the set of arbitration lines, in a particular arbitration phase for a particular transfer, and means, responsive to the local arbitration code and to other arbitration codes on the set of arbitration lines, for detecting an arbitration win for the particular transfer; address means, coupled to a set of address lines of the bus and to the local data processing module, responsive to the control means for selectively supplying addresses to, and sampling addresses on the set of address lines in address phases; data means, coupled to a set of data lines of the bus and to the local data processing module, responsive to the control means for selectively supplying data to, and sampling data on the set of data lines in data phases; wherein the arbitration phases, the address phases and the data phases are non-overlapping in time, and the set of arbitration lines is a subset of the set of address lines, and the set of address lines, is a subset of the set of data lines. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A bus interface for connection of a local data processing module to a bus, comprising:
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control means, coupled to the bus and the local data processing module, for detecting arbitration phases, address phases and data phases for transfers on the bus; arbitration logic, coupled to a set of arbitration lines of the bus and responsive to the control means, which arbitrates for transfers during arbitration phases, including means for supplying a local arbitration code to a first designated subset of the set of arbitration lines in a particular arbitration phase for a particular transfer, means for supplying a local priority code to a second designated subset of the set of arbitration lines in the particular arbitration phase, and means, responsive to the local arbitration code and the local priority code, and to other arbitration codes and priority codes on the set of arbitration lines, for detecting an arbitration win for the particular transfer during the particular arbitration phase; address means, coupled to a set of address lines of the bus and to the local data processing module, responsive to the control means for selectively supplying addresses to, and sampling addresses on the set of address lines in address phases; data means, coupled to a set of data lines of the bus and to the local data processing module, responsive to the control means for selectively supplying data to, and sampling data on the set of data lines in data phases; and bus request means, coupled to a bus request line on the bus, the means for detecting an arbitration win and the local data processing module, responsive to the control means for sampling bus request signals on the bus request line during bus phases, and supplying a bus request signal on the bus request line during a particular bus phase if the local data processing module signals a need for the bus and there was no previously asserted bus request signal on the bus from another module on the bus, or if a bus request signal was supplied by the bus request means during a preceding arbitration phase, the local data processing module continues to signal a need for the bus and an arbitration win is not detected, so that a multi-phase bus cycle is entered to serve a group of modules on the bus which assert the bus request signal during the particular bus phase; wherein the arbitration phases, the address phases and the data phases are non-overlapping in time, and the set of arbitration lines is a subset of the set of address lines, and the set of address lines is a subset of the set of data lines. - View Dependent Claims (22, 23, 24, 25)
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Specification