Computer architecture system having an imporved memory

• US 5,459,846 A
• Filed: 12/02/1988
• Issued: 10/17/1995
• Est. Priority Date: 12/02/1988
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/279,592
• Time in Patent Office: 2,510 Days
• Field of Search: 364/200, 364/900, 364/724.01, 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/200, 395/250, 395/375, 395/400, 395/425, 395/550, 395/800
• US Class Current: 711/214
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/23094 Debounce key
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 : Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35381 : Convert in real time input peripheral data to processor data, ouput data format
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/35588 : Pack, compress data efficiently in memory
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36227 : Assist operator to calculate unknown points, contours
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36395 : Load local computer program from host, data transfer ram to rom, BTR
• CPC Class Codes: G05B 2219/36502 : Ram for variable servo data, rom for fixed servo routine
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36506 : Store in Rom and Ram
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 12/0215 : with look ahead addressing means
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G09G 5/18 : Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/0033 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03H 17/0291 : Digital and sampled data filters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A computer system having an improved memory architecture uses a variety of memory speed enhancement features that can be used in combination. For example, the memory is scanned out across memory blocks, unnecessary row addressing operations are detected and eliminated, and the memory is organized to reduce row addressing operations for combinations of instruction accesses interspersed by operand accesses. In a DRAM configuration, unnecessary CAS addressing cycles and RAS addressing cycles are detected and eliminated. A memory address detector circuit in the memory controller determines the nature of the memory cycle; chip select, RAS, or CAS; needed to access stored digital information and deletes unnecessary cycles.

Claims

1. A computer system comprising:

a first memory storing first computer instructions and first computer operands;

a second memory storing second computer instructions and second computer operands;

a shared address generator circuit generating a shared memory address;

a first memory selection detector coupled to the shared address generator circuit and generating a first memory selection detector signal in response to the shared memory address;

a second memory selection detector coupled to the shared address generator circuit and generating a second memory selection detector signal in response to the shared memory address;

a first memory accessing circuit coupled to the first memory, to the shared address generator circuit, and to the first memory selection detector and accessing first computer instructions and first computer operands stored by the first memory in response to the shared memory address and in response to the first memory selection detector signal;

a second memory accessing circuit coupled to the second memory, to the shared address generator circuit, and to the second memory selection detector and accessing second computer instructions and second computer operands stored by the second memory in response to the shared memory address and in response to the second memory selection detector signal; and

a stored program computer coupled to the first memory accessing circuit and to the second memory accessing circuit and processing the accessed first computer operands and the accessed second computer operands in response to the accessed first computer instructions and in response to the accessed second computer instructions.

2. A computer system as set forth in claim 1, further comprising:

a third memory storing third computer instructions and third computer operands;

a third memory selection detector coupled to the shared address generator circuit and generating a third memory selection detector signal in response to the shared memory address; and

a third memory accessing circuit coupled to the third memory, to the shared address generator circuit, and to the third memory selection detector and accessing third computer instructions and third computer operands stored by the third memory in response to the shared memory address and in response to the third memory selection detector signal;

wherein the stored program computer is further coupled to the third memory accessing circuit and processing the accessed third computer operands in response to the accessed first computer instructions, in response to the accessed second computer instructions, and in response to the third computer instructions.

3. A computer system as set forth in claim 2, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

4. A computer system as set forth in claim 1, further comprising:

a third memory storing third computer instructions and third computer operands;

a forth memory storing forth computer instructions and forth computer operands;

a third memory selection detector coupled to the shared address generator circuit and generating a third memory selection detector signal in response to the shared memory address;

a forth memory selection detector coupled to the shared address generator circuit and generating a forth memory selection detector signal in response to the shared memory address;

a third memory accessing circuit coupled to the third memory, to the shared address generator circuit, and to the third memory selection detector and accessing third computer instructions and third computer operands stored by the third memory in response to the shared memory address and in response to the third memory selection detector signal; and

a forth memory accessing circuit coupled to the forth memory, to the shared address generator circuit, and to the forth memory selection detector and accessing forth computer instructions and forth computer operands stored by the forth memory in response to the shared memory address and in response to the forth memory selection detector signal;

wherein the stored program computer is further coupled to the third memory accessing circuit and processing the accessed third computer operands in response to the accessed first computer instructions, in response to the accessed second computer instructions, and in response to the accessed third computer instructions.

5. A computer system as set forth in claim 4, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

6. A computer system as set forth in claim 1, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the update detector and updating the shared memory address in response to the update detector signal.

7. A computer system as set forth in claim 6, further comprising:

a third memory storing third computer instructions and third computer operands;

a third memory selection detector coupled to the shared address generator circuit and generating a third memory selection detector signal in response to the shared memory address; and

a third memory accessing circuit coupled to the third memory, to the shared address generator circuit, and to the third memory selection detector and accessing third computer instructions and third computer operands stored by the third memory in response to the shared memory address and in response to the third memory selection detector signal;

wherein the stored program computer is further coupled to the third memory accessing circuit and processing the accessed third computer operands in response to the accessed first computer instructions, in response to the accessed second computer instructions, and in response to the accessed third computer instructions.

8. A computer system as set forth in claim 6, further comprising:

a third memory storing third computer instructions and third computer operands;

a forth memory storing forth computer instructions and forth computer operands;

a third memory selection detector coupled to the shared address generator circuit and generating a third memory selection detector signal in response to the shared memory address;

a forth memory selection detector coupled to the shared address generator circuit and generating a forth memory selection detector signal in response to the shared memory address;

a third memory accessing circuit coupled to the third memory, to the shared address generator circuit, and to the third memory selection detector and accessing third computer instructions and third computer operands stored by the third memory in response to the shared memory address and in response to the third memory selection detector signal; and

a forth memory accessing circuit coupled to the forth memory, to the shared address generator circuit, and to the forth memory selection detector and accessing forth computer instructions and forth computer operands stored by the forth memory in response to the shared memory address and in response to the forth memory selection detector signal;

wherein the stored program computer is further coupled to the third memory accessing circuit and to the forth memory accessing circuit and processing the accessed third computer operands and the accessed forth computer operands in response to the accessed first computer instructions, in response to the accessed second computer instructions, in response to the accessed third computer instructions, and in response to the accessed forth computer instructions.

9. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

a shared address generator circuit generating a shared memory address;

a plurality of memory selection detectors coupled the shared address generator circuit and generating a plurality of memory selection detector signals in response to the shared memory address;

a plurality of memory accessing circuits coupled to the plurality of memories, to the shared address generator circuit, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the shared memory address and in response to the plurality of memory selection detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

10. A computer system as set forth in claim 9, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the update detector and updating the shared memory address in response to the update detector signal.

11. A computer system as set forth in claim 9, further comprising:

a plurality of update detectors coupled to the shared address generator circuit and generating a plurality of update detector signals in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the plurality of update detectors and updating the shared memory address in response to the plurality of update detector signals.

12. A computer system as set forth in claim 9, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signal; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

13. A computer system as set forth in claim 9, further comprising:

a plurality of update detectors coupled to the shared address generator circuit and generating a plurality of update detector signals in response to the shared memory address;

a delay circuit coupled to the plurality of update detectors and generating a delay signal in response to the plurality of update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

14. A computer system as set forth in claim 9, further comprising:

a plurality of update detectors coupled to the shared address generator circuit and generating a plurality of update detector signals in response to the shared memory address;

a plurality of delay circuits coupled to the plurality of update detectors and generating a plurality of delay signals in response to the plurality of update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the plurality of delay circuits and updating the shared memory address in response to the plurality of delay signals.

15. A computer system as set forth in claim 9, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

16. A computer system comprising:

an instruction memory storing computer instructions;

an operand memory storing computer operands;

a shared address generator circuit generating a shared memory address;

an instruction memory selection detector coupled to the shared address generator circuit and generating an instruction memory selection detector signal in response to the shared memory address;

an operand memory selection detector coupled to the shared address generator circuit and generating an operand memory selection detector signal in response to the shared memory address;

an instruction memory accessing circuit coupled to the instruction memory, to the shared address generator circuit, and to the instruction memory selection detector and accessing instructions stored by the instruction memory in response to the shared memory address and in response to the instruction memory selection detector signal;

an operand memory accessing circuit coupled to the operand memory, to the shared address generator circuit, and to the operand memory selection detector and accessing operands stored by the operand memory in response to the shared memory address and in response to the operand memory selection detector signal; and

a stored program computer coupled to the instruction memory accessing circuit and to the operand memory accessing circuit and processing the operands accessed by the operand memory accessing circuit in response to the instructions accessed by the instruction memory accessing circuit.

17. A computer system as set forth in claim 16, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the update detector and updating the shared memory address in response to the update detector signal.

18. A computer system as set forth in claim 16, further comprising:

a plurality of update detectors coupled to the shared address generator circuit and generating a plurality of update detector signals in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the plurality of update detectors and updating the shared memory address in response to the plurality of update detector signals.

19. A computer system as set forth in claim 16, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signal; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

20. A computer system as set forth in claim 16, further comprising:

a plurality of update detectors coupled to the shared address generator circuit and generating a plurality of update detector signals in response to the shared memory address;

a delay circuit coupled to the plurality of update detectors and generating a delay signal in response to the plurality of update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

21. A computer system as set forth in claim 16, further comprising:

a plurality of update detectors coupled to the shared address generator circuit and generating a plurality of update detector signals in response to the shared memory address;

a plurality of delay circuits coupled to the plurality of update detectors and generating a plurality of delay signals in response to the plurality of update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the plurality of delay circuits and updating the shared memory address in response to the plurality of delay signals.

22. A computer system comprising:

a plurality of operand memories storing computer operands;

an instruction memory storing computer instructions;

a shared address generator circuit generating a shared memory address;

a plurality of operand memory selection detectors coupled to the shared address generator circuit and generating a plurality of operand memory selection detector signals in response to the shared memory address;

an instruction memory selection detector coupled to the shared address generator circuit and generating an instruction memory selection detector signal in response to the shared memory address;

an operand memory accessing circuit coupled to the plurality of operand memories, to the shared address generator circuit, and to the plurality of operand memory selection detectors and accessing operands stored by the plurality of operand memories in response to the shared memory address and in response to the plurality of operand memory selection detector signals;

an instruction memory accessing circuit coupled to the instruction memory, to the shared address generator circuit, and to the instruction memory selection detector and accessing computer instructions stored by the instruction memory in response to the shared memory address and in response to the instruction memory selection detector signal; and

a stored program computer coupled to the instruction memory accessing circuit and to the operand memory accessing circuit and processing the operands accessed by the operand memory accessing circuit in response to the instructions accessed by the instruction memory accessing circuit.

23. A computer system as set forth in claim 22, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the update detector and updating the shared memory address in response to the update detector signal.

24. A computer system as set forth in claim 22, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

25. A computer system comprising:

a memory storing computer instructions and computer operands;

a memory address generator circuit generating a memory address having a plurality of digital memory address bits including a first digital memory address bit and a second digital memory address bit;

a first detector circuit coupled to the memory address generator circuit and generating a first detector signal in response to detection of a change in the first digital memory address bit;

a second detector circuit coupled to the memory address generator circuit and generating a second detector signal in response to detection of a change in the second digital memory address bit;

a time delay circuit coupled to the first detector circuit-and to the second detector circuit and generating a time delay signal in response to the first detector signal and in response to the second detector signal;

an update circuit coupled to the memory address generator circuit and to the time delay circuit and updating the plurality of digital memory address bits in response to the time delay signal;

an accessing circuit coupled to the memory and to the memory address generator circuit and accessing computer instructions and computer operands stored by the memory in response to the memory address; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

26. A computer system as set forth in claim 25, wherein the first detector circuit includes a first overflow detector circuit generating the first detector signal in response to detection of the change in the first digital memory address bit as an overflow to the first digital memory address bit and wherein the second detector circuit includes a second overflow detector circuit generating the second detector signal in response to detection of the change in the second digital memory address bit as an overflow to the second digital memory address bit.

27. A computer system as set forth in claim 25, wherein the first detector circuit includes a first storing circuit coupled to the memory address generator circuit and storing the first digital memory address bit and a first comparitor circuit coupled to the storing circuit and to the memory address generator circuit and generating the first detector signal in response to detection of the change in the first digital memory address bit by comparing the first digital memory address bit stored by the first storing circuit and the first digital memory address bit included in the memory address generated by the memory address generator circuit and wherein the second detector circuit includes a second storing circuit coupled to the memory address generator circuit and storing the second digital memory address bit and a second comparitor circuit coupled to the second storing circuit and to the memory address generator circuit and generating the second detector signal in response to detection of the change in the second digital memory address bit by comparing the second digital memory address bit stored by the storing circuit and the second digital memory address bit included in the memory address generated by the memory address generator circuit.

28. A computer system comprising:

a memory storing a plurality of operand data bits;

an address generator generating a memory address;

a detector coupled to the address generator and generating a detector signal identifying a readdressing condition or a scanout condition in response to the memory address;

a time delay circuit generating a readdressing time delay in response to the detector signal identifying a readdressing condition and not generating the readdressing time delay in response to the detector signal identifying a scanout condition;

a memory accessing circuit coupled to the memory, to the address generator, and to the time delay circuit and accessing at least one readdressed operand data bit in response to the memory address having a readdressing time delay and accessing at least one scanout operand data bit in response to the memory address without having a readdressing time delay; and

a stored program digital computer coupled to the memory accessing circuit and processing the operand data bits in response to execution of computer instructions.

29. A computer system as set forth in claim 28, wherein the address generator includes an address counter generating a first plurality of memory address bits and a bit counter having a second plurality of address bits;

wherein the detector generates the detector signal identifying the readdressing condition and identifying the scanout condition in response to the second plurality of address bits;

wherein the time delay circuit generates the readdressing time delay as a gated clock signal delay in response to the detector signal identifying a readdressing condition.

30. A computer system as set forth in claim 28, wherein the memory includes a dynamic random access memory storing the plurality of operand data bits and wherein said system further comprises a refresh circuit coupled to the dynamic random access memory and to the stored program digital computer and refreshing the plurality of operand data bits stored by the dynamic random access memory in response to the processing by the stored program computer.

31. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator generating a memory address;

a plurality of memory selection detectors coupled to the address generator and generating a plurality of memory selection detector signals in response to the memory address;

a memory accessing circuit coupled to the plurality of memories, to the address generator, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

a plurality of update detectors coupled to the address generator and generating a plurality of update detector signals in response to the memory address;

an address update circuit coupled to the address generator and to the plurality of update detectors and updating the memory address in response to the plurality of update detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

32. A computer system as set forth in claim 31, wherein each of the plurality of memory selection detectors includes:

a register storing a selection address and

a comparitor circuit coupled to the address generator and to the register and generating at least one of the memory selection detector signals in response to comparison of the memory address generated by the address generator and the selection address.

33. In a computer system comprising a stored program digital computer and a memory, a process comprising:

generating a memory address;

detecting a readdressing condition;

causing a time delay in response to the detecting of the readdressing condition;

accessing the memory in response to the memory address and in response to the time delay;

detecting a scanout condition;

accessing the memory in response to the memory address and not in response to the time delay; and

processing data accessed by the accessing step in response to a stored program.

34. In a computer system comprising a stored program digital computer and a memory, the process as set forth in claim 33 further comprising:

causing the time delay by gating a clock pulse and

accessing the memory in response to the clock pulse.

35. A computer system comprising:

a memory storing operands;

an address circuit generating a memory address having readdressing address bits and having scanout address bits;

a detector circuit coupled to the address circuit and generating a detector signal having a readdressing state and a scanout state in response to the memory address;

a readdressing access circuit coupled to the memory, to the addressing circuit, and to the detector circuit and simultaneously accessing a plurality of operand bits in response to the readdressing address bits;

a scanout access circuit coupled to the readdressing access circuit and to the addressing circuit and sequentially accessing a plurality of the simultaneously accessed operand bits in response to the scanout address bits; and

a stored program computer coupled to the scanout access circuit and processing the sequentially accessed operand bits in response to at least one stored instruction.

36. A computer system as set forth in claim 35, wherein the memory includes a dynamic random access memory storing the operands and wherein said system further comprises a refresh circuit coupled to the dynamic random access memory and to the stored program computer and refreshing the operands stored by the dynamic random access memory in response to the processing by the stored program computer.

37. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator circuit generating a memory address having less significant address bits and having more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator circuit and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a detector coupled to the address generator circuit and generating a detector signal in response to a change in the more significant address bits;

a delay circuit coupled to the detector and generating a time delay signal in response to the detector signal;

an address update circuit coupled to the address generator circuit and to the delay circuit and updating the memory address in response to the time delay signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

38. A computer system as set forth in claim 37,

wherein the first detector includes

a first register coupled to the address generator and storing the more significant bits of the memory address and

a first comparitor circuit coupled to the address generator and to the first register and generating the first detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the more significant bits of the memory address stored by the first register and

wherein the second detector includes

a second register coupled to the address generator and storing the middle significant bits of the memory address and

a second comparitor circuit coupled to the address generator and to the second register and generating the second detector signal in response to comparison of the middle significant bits of the memory address generated by the address generator and the middle significant bits of the memory address stored by the second register.

39. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a plurality of detectors coupled to the address generator and generating a plurality of detector signals in response to the memory address;

an address update circuit coupled to the address generator and to the plurality of detectors and updating the memory address in response to the plurality of detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

40. A computer system as set forth in claim 39, wherein each of the plurality of detectors includes:

a register coupled to the address generator and storing a portion of but not all of the memory address and

a comparitor circuit coupled to the address generator and to the register and generating at least one of the detector signals in response to comparison of the memory address generated by the address generator and the portion of the memory address stored by the register.

41. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator circuit generating a memory address having more significant address bits, middle significant address bits, and less significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator circuit and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a first detector coupled to the address generator circuit and generating a first detector signal in response to the more significant address bits of the memory address;

a second detector coupled to the address generator circuit and generating a second detector signal in response to the middle significant address bits of the memory address;

a first delay circuit coupled to the first detector and generating a first time delay signal in response to the first detector signal;

a second delay circuit coupled to the second detector and generating a second time delay signal in response to the second detector signal;

an address update circuit coupled to the address generator circuit, to the first delay circuit, and to the second delay circuit and updating the memory address in response to the first time delay signal and in response to the second time delay signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

42. A computer system as set forth in claim 41,

wherein the first detector includes

a first register coupled to the address generator and storing the more significant bits of the memory address and

a first comparitor circuit coupled to the address generator and to the first register and generating the first detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the more significant bits of the memory address stored by the first register and

wherein the second detector includes

a second register coupled to the address generator and storing the middle significant bits of the memory address and

a second comparitor circuit coupled to the address generator and to the second register and generating the second detector signal in response to comparison of the middle significant bits of the memory address generated by the address generator and the middle significant bits of the memory address stored by the second register.

43. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a plurality of detectors coupled to the address generator and generating a plurality of detector signals in response to the memory address;

an address update circuit coupled to the address generator and to the plurality of detectors and updating the memory address in response to the plurality of detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

44. A computer system as set forth in claim 43, wherein each of the plurality of detectors includes:

a register coupled to the address generator and storing a portion of but not all of the memory address and

a comparitor circuit coupled to the address generator and to the register and generating at least one of the detector signals in response to comparison of the memory address generated by the address generator and the portion of the memory address stored by the register.

45. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a plurality of detectors coupled to the address generator and generating a plurality of detector signals in response to the more significant address bits;

a time delay circuit coupled to the plurality of detectors and generating a time delay signal in response to the plurality of detector signals;

an address update circuit coupled to the address generator and to the time delay circuit and updating the memory address in response to the time delay signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

46. A computer system as set forth in claim 45, wherein each of the plurality of detectors includes:

a register coupled to the address generator and storing the more significant address bits and

a comparitor circuit coupled to the address generator and to the register and generating at least one of the detector signals in response to comparison of the memory address generated by the address generator and the more significant address bits stored by the register.

47. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits, middle significant address bits, and more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a first detector coupled to the address generator and generating a first detector signal in response to detection of a change in the middle significant address bits;

a second detector coupled to the address generator and generating a second detector signal in response to detection of a change in the more significant address bits;

an internal scanout update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a first address update rate in response to a first condition of the first detector signal and the second detector signal;

an external scanout update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a second address update rate that is lower than the first address update rate in response to a second condition of the first detector signal and the second detector signal;

a re-addressing address update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a third address update rate that is lower than the first address update rate and that is lower than the second address update rate in response to a third condition of the first detector signal and the second detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

48. A computer system as set forth in claim 47,

wherein the first detector includes

a first register coupled to the address generator and storing the middle significant bits of the memory address and

a first comparitor circuit coupled to the address generator and to the first register and generating the first detector signal in response to comparison of the middle significant bits of the memory address generated by the address generator and the middle significant bits of the memory address stored by the first register and

wherein the second detector includes

a second register coupled to the address generator and storing the more significant bits of the memory address and

a second comparitor circuit coupled to the address generator and to the second register and generating the second detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the more significant bits of the memory address stored by the second register.

49. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator circuit generating a memory address;

a plurality of memory selection detectors coupled to the address generator circuit and generating a plurality of memory selection detector signals in response to the memory address;

a plurality of memory accessing circuits coupled to the plurality of memories, to the address generator circuit, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

an update detector coupled to the address generator circuit and generating an update detector signal in response to the memory address;

an address update circuit coupled to the address generator circuit and to the update detector and updating the memory address in response to the update detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

50. A computer system as set forth in claim 49, wherein each of the plurality of memory selection detectors includes:

a register storing a selection address and

a comparitor circuit coupled to the address generator and to the register and generating at least one of the memory selection detector signals in response to comparison of the memory address generated by the address generator and the selection address.

51. A computer system comprising:

an instruction memory storing computer instructions;

an operand memory storing computer operands;

an address generator generating a memory address;

an instruction address detector circuit coupled to the address generator and generating an instruction address detector signal in response to the more significant address bits of the memory address;

an operand detector circuit coupled to the address generator and generating an operand detector signal in response to the more significant address bits of the memory address;

an instruction accessing circuit coupled to the instruction memory, to the address generator, and to the instruction detector and accessing computer instructions stored by the instruction memory in response to the memory address and in response to the instruction detector signal;

an operand accessing circuit coupled to the operand memory, to the address generator, and to the operand detector and accessing computer operands stored by the operand memory in response to the memory address and in response to the operand detector signal;

a stored program digital computer coupled to the instruction accessing circuit and to the operand accessing circuit and processing the computer operands accessed by the operand accessing circuit in response to the computer instructions accessed by the instruction accessing circuit;

an address update detector coupled to the address generator and generating an address update detector signal in response to the more Significant address bits of the memory address; and

an address update circuit coupled to the address generator and to the address update detector and updating the address in response to the address update detector signal.

52. A computer system as set forth in claim 51,

wherein the instruction address detector circuit includes

an instruction address register storing an instruction detector address and

an instruction address comparitor circuit coupled to the address generator and to the instruction address register and generating the instruction address detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the instruction detector address and

wherein the operand detector circuit includes

an operand address register storing an operand detector address and

an operand address comparitor circuit coupled to the address generator and to the operand address register and generating the operand detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the operand detector address.

53. A computer system comprising:

an instruction memory storing computer instructions;

an operand memory storing computer operands;

an address generator circuit generating a memory address;

an instruction detector coupled to the address generator circuit and generating an instruction detector signal in response to the memory address;

an operand detector coupled to the address generator circuit and generating an operand detector signal in response to the memory address;

an instruction accessing circuit coupled to the instruction memory, to the address generator circuit, and to the instruction detector and accessing computer instructions stored by the instruction memory in response to the memory address and in response to the instruction detector signal;

an operand accessing circuit coupled to the operand memory, to the address generator circuit, and to the operand detector and accessing computer operands stored by the operand memory in response to the memory address and in response to the operand detector signal;

a stored program digital computer coupled to the instruction accessing circuit and to the operand accessing circuit and processing the computer operands accessed by the operand accessing circuit in response to the computer instructions accessed by the instruction accessing circuit;

an address update detector coupled to the address generator and generating an address update detector signal in response to the memory address;

a delay circuit coupled to the address update detector and generating a time delay signal in response to the address update detector signal; and

an address update circuit coupled to the address generator circuit and to the delay circuit and updating the memory address in response to the time delay signal.

54. A computer system as set forth in claim 53,

wherein the instruction detector includes

an instruction address register storing an instruction detector address and

an instruction address comparitor circuit coupled to the address generator and to the instruction address register and generating the instruction detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the instruction detector address and

wherein the operand detector includes

an operand address register storing an operand detector address and

a operand address comparitor circuit coupled to the address generator and to the operand address register and generating the operand detector signal in response to comparison of the more significant bits of the memory address generated by the address generator and the operand detector address.

55. A computer system comprising:

a plurality of instruction memories storing computer instructions;

an operand memory storing computer operands;

a shared address generator circuit generating a shared memory address;

a plurality of instruction memory selection detectors coupled to the shared address generator circuit and generating a plurality of instruction memory selection detector signals in response to the shared memory address;

an operand memory selection detector coupled to the shared address generator circuit and generating an operand memory selection detector signal in response to the shared memory address;

an instruction memory accessing circuit coupled to the plurality of instruction memories, to the shared address generator circuit, and to the plurality of instruction memory selection detectors and accessing instructions stored by the plurality of instruction memories in response to the shared memory address and in response to the plurality of instruction memory selection detector signals;

an operand memory accessing circuit coupled to the operand memory, to the shared address generator circuit, and to the operand memory selection detector and accessing computer operands stored by the operand memory in response to the shared memory address and in response to the operand memory selection detector signal; and

a stored program computer coupled to the instruction memory accessing circuit and to the operand memory accessing circuit and processing the operands accessed by the operand memory accessing circuit in response to the instructions accessed by the instruction memory accessing circuit.

56. A computer system as set forth in claim 55, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address; and

an address update circuit coupled to the shared address generator circuit and to the update detector and updating the shared memory address in response to the update detector signal.

57. A memory system as set forth in claim 55, further comprising:

an update detector coupled to the shared address generator circuit and generating an update detector signal in response to the shared memory address;

a delay circuit coupled to the update detector and generating a delay signal in response to the update detector signals; and

an address update circuit coupled to the shared address generator circuit and to the delay circuit and updating the shared memory address in response to the delay signal.

58. In a computer system comprising a stored program digital computer and a memory, a process comprising:

generating a first memory address;

detecting a first condition of the first memory address;

invoking a time delay in response to detecting of the first condition of the memory address;

accessing a first stored instruction from the memory in response to the first memory address after the completion of the time delay;

executing the accessed first stored instruction;

generating a second memory address;

detecting a second condition of the second memory address;

not invoking a time delay in response to detecting of the second condition of the memory address;

accessing a second stored instruction from the memory in response to the second memory address without completion of the time delay; and

executing the accessed second stored instruction.

59. In a computer system comprising a stored program digital computer and a memory, the process set forth in claim 58 further comprising:

generating a third memory address;

detecting a third condition of the third memory address;

not invoking a time delay in response to detecting of the third condition of the memory address;

accessing a first operand from the memory in response to the third memory address without completion of the time delay; and

processing the accessed first operand in response to the executing of the second stored instruction.

60. In a computer system comprising a stored program digital computer and a plurality of memories, a process comprising:

generating a first memory address;

detecting a first condition of the first memory address;

invoking a time delay in response to detecting of the first condition of the memory address;

accessing a first stored instruction from at least one of the plurality of memories in response to the first memory address after the completion of the time delay;

executing the accessed first stored instruction;

generating a second memory address;

detecting a second condition of the second memory address;

not invoking a time delay in response to detecting of the second condition of the memory address;

accessing a second stored instruction from at least one of the plurality of memories in response to the second memory address without completion of the time delay; and

executing the accessed second stored instruction.

61. In a computer system comprising a stored program digital computer and a plurality of memories, the process set forth in claim 60 further comprising:

generating a third memory address;

detecting a third condition of the third memory address;

not invoking a time delay in response to detecting of the third condition of the memory address;

accessing a first operand from at least one of the plurality of memories in response to the third memory address without completion of the time delay; and

processing the accessed first operand in response to the executing of the second stored instruction.

62. A computer system comprising:

a first memory storing first digital data;

a second memory storing second digital data;

a third memory storing third digital data;

a forth memory storing forth digital data;

a memory address generator generating a memory address;

a first access circuit coupled to the first memory and accessing the first digital data;

a second access circuit coupled to the second memory and accessing the second digital data;

a third access circuit coupled to the third memory and accessing the third digital data;

a forth access circuit coupled to the forth memory and accessing the forth digital data;

a stored program digital computer coupled to the first access circuit, to the second access circuit, to the third access circuit, and to the forth access circuit and processing the accessed first digital data, the accessed second digital data, the accessed third digital data, and the accessed forth digital data;

a memory address update circuit coupled to the stored program digital computer and to the memory address generator and updating the memory address in response to the processing of the accessed first digital data, the accessed second digital data, the accessed third digital data, and the accessed forth digital data;

a first address detector coupled to the memory address generator and generating a first detector signal in response to a first condition of the memory address;

a second address detector coupled to the memory address generator and generating a second detector signal in response to a second condition of the memory address;

a third address detector coupled to the memory address generator and generating a third detector signal in response to a third condition of the memory address;

a forth address detector coupled to the memory address generator and generating a forth detector signal in response to a forth condition of the memory address; and

a delay circuit coupled to the stored program digital computer, to the first address detector, to the second address detector, to the third address detector, and to the forth address detector and delaying the processing by the stored program digital computer in response to the first detector signal, the second detector signal, the third detector signal, and the forth detector signal.

63. A computer system comprising:

a first memory storing first computer instructions;

a second memory storing second computer instructions;

a third memory storing third computer instructions;

a forth memory storing forth computer instructions;

a memory address generator generating a memory address;

a first access circuit coupled to the first memory and accessing the first computer instructions;

a second access circuit coupled to the second memory and accessing the second computer instructions;

a third access circuit coupled to the third memory and accessing the third computer instructions;

a forth access circuit coupled to the forth memory and accessing the forth computer instructions;

a stored program digital computer coupled to the first access circuit, to the second access circuit, to the third access circuit, and to the forth access circuit and processing digital data in response to the accessed first computer instructions, the accessed second computer instructions, the accessed third computer instructions, and the accessed forth computer instructions;

a memory address update circuit coupled to the stored program digital computer and to the memory address generator and updating the memory address in response to the processing of the digital data;

a first address detector coupled to the memory address generator and generating a first detector signal in response to a first condition of the memory address;

a second address detector coupled to the memory address generator and generating a second detector signal in response to a second condition of the memory address;

a third address detector coupled to the memory address generator and generating a third detector signal in response to a third condition of the memory address;

a forth address detector coupled to the memory address generator and generating a forth detector signal in response to a forth condition of the memory address; and

a delay circuit coupled to the stored program digital computer, to the first address detector, to the second address detector, to the third address detector, and to the forth address detector and delaying the processing by the stored program digital computer in response to the first detector signal, the second detector signal, the third detector signal, and the forth detector signal.

64. A computer system comprising:

a first memory storing first computer instructions;

a second memory storing second computer instructions;

a third memory storing third computer instructions;

a forth memory storing forth computer instructions;

a memory address generator generating a memory address;

a first access circuit coupled to the first memory and accessing the first computer instructions;

a second access circuit coupled to the second memory and accessing the second computer instructions;

a third access circuit coupled to the third memory and accessing the third computer instructions;

a forth access circuit coupled to the forth memory and accessing the forth computer instructions;

a stored program digital computer coupled to the first access circuit, to the second access circuit, to the third access circuit, and to the forth access circuit and processing digital data in response to the accessed first computer instructions, the accessed second computer instructions, the accessed third computer instructions, and the accessed forth computer instructions;

a memory address update circuit coupled to the stored program digital computer and to the memory address generator and updating the memory address in response to the processing of the digital data;

a first readdressing-address detector coupled to the more significant bits of the memory address generator and generating a first readdressing detector signal in response to a condition of the more significant bits of the memory address;

a second readdressing address detector coupled to the more significant bits of the memory address generator and generating a second readdressing detector signal in response to a condition of the more significant bits of the memory address;

a third readdressing address detector coupled to the more significant bits of the memory address generator and generating a third readdressing detector signal in response to a condition of the more significant bits of the memory address;

a forth readdressing address detector coupled to the more significant bits of the memory address generator and generating a forth readdressing detector signal in response to a condition of the more significant bits of the memory address;

a first scanout address detector coupled to the less significant bits of the memory address generator and generating a first scanout detector signal in response to a condition of the less significant bits of the memory address;

a second scanout address detector coupled to the less significant bits of the memory address generator and generating a second scanout detector signal in response to a condition of the less significant bits of the memory address;

a third scanout address detector coupled to the less significant bits of the memory address generator and generating a third scanout detector signal in response to a condition of the less significant bits of the memory address;

a forth scanout address detector coupled to the less significant bits of the memory address generator and generating a forth scanout detector signal in response to a condition of the less significant bits of the memory address; and

a readdressing delay circuit coupled to the stored program digital computer, to the first readdressing address detector, to the second readdressing address detector, to the third readdressing address detector, and to the forth readdressing address detector and delaying the processing by the stored program digital computer by a readdressing delay period in response to the first readdressing detector signal, to the second readdressing detector signal, to the third readdressing detector signal, and to the forth readdressing detector signal; and

a scanout delay circuit coupled to the stored program digital computer, to the first scanout address detector, to the second scanout address detector, to the third scanout address detector, and to the forth scanout address detector and delaying the processing by the stored program digital computer by a scanout delay period in response to the first scanout detector signal, to the second scanout detector signal, to the third scanout detector signal, and to the forth scanout detector signal.

65. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having more significant address bits and having less significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a detector register coupled to the address generator and storing the more significant address bits of the memory address;

a detector circuit coupled to the address generator and to the detector register and generating a detector signal in response to comparison of the more significant address bits of the memory address generated by the address generator and the more significant address bits of the memory address stored by the detector register;

an address update circuit coupled to the address generator and to the detector circuit and updating the memory address in response to the detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

66. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator circuit generating a memory address having more significant address bits, middle significant address bits, and less significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator circuit and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a first detector coupled to the address generator circuit and generating a first detector signal in response to the more significant address bits of the memory address;

a second detector coupled to the address generator circuit and generating a second detector signal in response to the middle significant address bits of the memory address;

a first delay circuit coupled to the first detector and generating a first time delay signal in response to the first detector signal;

a second delay circuit coupled to the second detector and generating a second time delay signal in response to the second detector signal;

an address update circuit coupled to the address generator circuit, to the first delay circuit, and to the second delay circuit and updating the memory address in response to the first time delay signal and in response to the second time delay signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

67. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having a plurality of data bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a plurality of detector registers each storing a plurality of bits of the memory address;

a plurality of comparitor detectors coupled to the address generator and to the plurality of detector registers and each comparitor detector generating a detector signal in response to comparison of the memory address and the plurality of bits of the memory address stored by a detector register;

an address update circuit coupled to the address generator and to the comparitor detectors and updating the memory address in response to the detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

68. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a plurality of detectors coupled to the address generator and generating a plurality of detector signals in response to the more significant address bits;

a time delay circuit coupled to the plurality of detectors and generating a time delay signal in response to the plurality of detector signals;

an address update circuit coupled to the address generator and to the time delay circuit and updating the memory address in response to the time delay signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

69. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a comparitor detector coupled to the address generator and generating a detector signal in response to detection of a change in the more significant address bits of the memory address;

an address update circuit coupled to the address generator and to the comparitor detector and updating the memory address in response to the detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

70. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a detector coupled to the address generator and generating a re-addressing detector signal in response to detection of a change in the more significant address bits;

a scanout address update circuit coupled to the address generator and to the detector and updating the memory address at a first address update rate in response to a first state of the re-addressing detector signal;

a re-addressing address update circuit coupled to the address generator and to the detector and updating the memory address at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

71. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits, middle significant address bits, and more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a first detector coupled to the address generator and generating a first detector signal in response to detection of a change in the middle significant address bits;

a second detector coupled to the address generator and generating a second detector signal in response to detection of a change in the more significant address bits;

an internal scanout update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a first address update rate in response to a first condition of the first detector signal and the second detector signal;

an external scanout update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a second address update rate that is lower than the first address update rate in response to a second condition of the first detector signal and the second detector signal;

a re-addressing address update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a third address update rate that is lower than the first address update rate and that is lower than the second address update rate in response to a third condition of the first detector signal and the second detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

72. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having more significant address bits and having less significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a detector register coupled to the address generator and storing the more significant address bits of the memory address;

a detector circuit coupled to the address generator and to the detector register and generating a detector signal in response to comparison of the more significant address bits of the memory address generated by the address generator and the more significant address bits of the memory address stored by the detector register;

an address update circuit coupled to the address generator and to the detector circuit and updating the address in response to the detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

73. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator circuit generating a memory address having less significant address bits and having more significant address bits;

a memory accessing circuit coupled to the random access memory and to the address generator circuit and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a detector coupled to the address generator circuit and generating a detector signal in response to a change in the more significant address bits;

a delay circuit coupled to the detector and generating a time delay signal in response to the detector signal;

an address update circuit coupled to the address generator circuit and to the delay circuit and updating the memory address in response to the time delay signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

74. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address having a plurality of data bits;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a plurality of detector registers each storing a plurality of bits of the memory address;

a plurality of comparitor detectors coupled to the address generator and to the plurality of detector registers and each comparitor detector generating a detector signal in response to comparison of the memory address and the plurality of bits of the memory address stored by a detector register;

an address update circuit coupled to the address generator and to the comparitor detectors and updating the memory address in response to the detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

75. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a comparitor detector coupled to the address generator and generating a detector signal in response to detection of a change in the memory address;

an address update circuit coupled to the address generator and to the comparitor detector and updating the memory address; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

76. A computer system comprising:

a random access memory storing computer instructions and computer operands;

an address generator generating a memory address;

a memory accessing circuit coupled to the random access memory and to the address generator and accessing computer instructions and computer operands stored by the random access memory in response to the memory address;

a detector coupled to the address generator and generating a detector signal in response to detection of a change in the more significant address bits;

a scanout address update circuit coupled to the address generator and to the detector and updating the memory address at a first address update rate in response to a first state of the detector signal;

a re-addressing address update circuit coupled to the address generator and to the detector and updating the memory address at a second address update rate that is lower than the first address update rate in response to a second state of the detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

77. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator generating a memory address having a plurality of data bits;

a plurality of memory selection detectors coupled to the address generator and generating a plurality of memory selection detector signals in response to the memory address;

a memory accessing circuit coupled to the plurality of memories, to the address generator, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

a plurality of detector registers each coupled to the address generator and each storing a plurality of bits of the memory address;

a plurality of comparitor detectors coupled to the address generator and to the plurality of detector registers and each comparitor detector generating an update detector signal in response to comparison of the memory address generated by said address generator and the plurality of bits of the memory address stored by a detector register;

an address update circuit coupled to the address generator and to the plurality of comparitor detectors and updating the memory address in response to the update detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

78. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a plurality of memory selection detectors coupled to the address generator and generating a plurality of memory selection detector signals in response to the memory address;

a memory accessing circuit coupled to the plurality of memories, to the address generator, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

a plurality of update detectors coupled to the address generator and generating a plurality of update detector signals in response to the more significant address bits;

a plurality of time delay circuits coupled to the plurality of update detectors and generating a plurality of time delay signals in response to the plurality of update detector signals;

an address update circuit coupled to the address generator and to the plurality of time delay circuits and updating the memory address in response to the plurality of time delay signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

79. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a plurality of memory selection detectors coupled to the address generator and generating a plurality of memory selection detector signals in response to the memory address;

a memory accessing circuit coupled to the plurality of memories, to the address generator, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

an update detector coupled to the address generator and generating an update detector signal in response to detection of a change in the more significant address bits;

a scanout address update circuit coupled to the address generator and to the update detector and updating the memory address at a first address update rate in response to a first state of the update detector signal;

a re-addressing address update circuit coupled to the address generator and to the update detector and updating the memory address at a second address update rate that is lower than the first address update rate in response to a second state of the update detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

80. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits, middle significant address bits, and more significant address bits;

a plurality of memory selection detectors coupled to the address generator and generating a plurality of memory selection detector signals in response to the memory address;

a memory accessing circuit coupled to the plurality of memories, to the address generator, and to the plurality of memory selection detectors and accessing computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

a first detector coupled to the address generator and generating a first detector signal in response to detection of a change in the middle significant address bits;

a second detector coupled to the address generator and generating a second detector signal in response to detection of a change in the more significant address bits;

an internal scanout update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a first address update rate in response to a first condition of the first detector signal and the second detector signal;

an external scanout update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a second address update rate that is lower than the first address update rate in response to a second condition of the first detector signal and the second detector signal;

a re-addressing address update circuit coupled to the address generator, to the first detector, and to the second detector and updating the memory address at a third address update rate that is lower than the first address update rate and that is lower than the second address update rate in response to a third condition of the first detector signal and the second detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

81. A computer system comprising:

a memory storing computer instructions and computer operands;

an address circuit generating a memory address;

a first address detector circuit coupled to the address circuit and generating a first detector signal in response to a first condition of the memory address;

a second address detector circuit coupled to the address circuit and generating a first detector signal in response to a second condition of the memory address;

a memory accessing circuit coupled to the memory, to the address circuit, to the first address detector circuit, and to the second address detector circuit and accessing computer instructions and computer operands stored by the memory in response to the memory address, in response to the first detector signal, and in response to the second detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

82. A computer system comprising:

a memory storing computer instructions and computer operands;

an address circuit generating a memory address;

a plurality of address detector circuits coupled to the address circuit and generating a plurality of detector signals in response to the memory address;

a memory accessing circuit coupled to the memory, to the address circuit, and to the plurality of address detector circuits and accessing computer instructions and computer operands stored by the memory in response to the memory address and in response to the plurality of detector signals; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.

83. A computer system comprising:

a first memory storing first computer instructions and first computer operands;

a second memory storing second computer instructions and second computer operands;

an address circuit generating a memory address;

a first select circuit coupled to the first memory and to the address circuit and generating a first select signal in response to a first condition of the memory address;

a second select circuit coupled to the second memory and to the address circuit and generating a second select signal in response to a second condition of the memory address;

a first detector circuit coupled to the address circuit and generating a first detector signal in response to a first condition of the memory address;

a second detector circuit coupled to the address circuit and generating a second detector signal in response to a second condition of the memory address;

an update circuit coupled to the address circuit, to the first detector circuit, and to the second detector circuit and updating the memory address in response to the first detector signal and in response to the second detector signal;

a first access circuit coupled to the first memory, to the first select circuit, and to the address circuit and accessing first computer instructions and first computer operands from the first memory in response to the memory address and in response to the first select signal;

a second access circuit coupled to the second memory, to the second select circuit, and to the address circuit and accessing second computer instructions and second computer operands from the second memory in response to the memory address and in response to the second select signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed first computer operands and the second computer operands in response to the accessed first computer instructions and in response to the second computer instructions.

84. A computer system comprising:

a plurality of memories storing computer instructions and computer operands;

an address generator generating a memory address having less significant address bits and having more significant address bits;

a plurality of memory selection detectors coupled to the address generator and generating a plurality of memory selection detector signals in response to the more significant address bits;

a memory accessing circuit coupled to the plurality of memories, to the address generator, and to the plurality of memory selection detectors and accessing the computer instructions and computer operands stored by the plurality of memories in response to the memory address and in response to the plurality of memory selection detector signals;

a comparitor detector coupled to the address generator and generating a comparitor detector signal in response to detection of a change in the more significant address bits of the memory address;

an address update circuit coupled to the address generator and to the comparitor detector and updating the memory address in response to the comparitor detector signal; and

a stored program computer coupled to the memory accessing circuit and processing the accessed computer operands in response to the accessed computer instructions.