×

Process for high density flash EPROM cell

  • US 5,460,988 A
  • Filed: 04/25/1994
  • Issued: 10/24/1995
  • Est. Priority Date: 04/25/1994
  • Status: Expired due to Fees
First Claim
Patent Images

1. A method of forming a floating surrounding-gate memory cell, for an electrically programmable read-only memory (EPROM) or flash-memory, comprising the steps of:

  • forming a well in a silicon substrate by implantation of a first conductivity type dopant;

    forming silicon mesas from said well, by anisotropically etching portions of said device-well, wherein said mesas remain at the unetched portions of said device-well;

    forming source regions in said device-well in the regions between said silicon mesas, by implanting with a second and opposite conductivity type dopant to said first conductivity type dopant, and simultaneously forming drain regions in the top of said silicon mesas by said implanting with a second and opposite conductivity type dopant;

    forming a first oxide layer over horizontal and vertical surfaces of said silicon mesas and over said source regions;

    anisotropically etching said first oxide layer to remove said first oxide layer from all said horizontal surfaces;

    forming a second oxide layer over said silicon mesas, said first oxide layer and said source regions, whereby a gate oxide is formed along said vertical surfaces of said silicon mesas, and a tunnel oxide that is thinner than said gate oxide is formed over said source regions;

    forming a first conductive layer over said gate oxide, thereby creating said surrounding-gate for said floating memory cell;

    forming an interpoly dielectric layer over the vertical surfaces of said first conductive layer, and horizontally over said source regions; and

    forming a second conductive layer over said interpoly dielectric layer, which acts as a control gate and word line for said memory cell.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×