Process for high density flash EPROM cell

• US 5,460,988 A
• Filed: 04/25/1994
• Issued: 10/24/1995
• Est. Priority Date: 04/25/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hong, Gary
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/231,811
• Time in Patent Office: 547 Days
• Field of Search: 437/43, 437/48, 437/49, 437/52, 257/315, 257/316
• US Class Current: 438/259
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.

Claims

1. A method of forming a floating surrounding-gate memory cell, for an electrically programmable read-only memory (EPROM) or flash-memory, comprising the steps of:

forming a well in a silicon substrate by implantation of a first conductivity type dopant;

forming silicon mesas from said well, by anisotropically etching portions of said device-well, wherein said mesas remain at the unetched portions of said device-well;

forming source regions in said device-well in the regions between said silicon mesas, by implanting with a second and opposite conductivity type dopant to said first conductivity type dopant, and simultaneously forming drain regions in the top of said silicon mesas by said implanting with a second and opposite conductivity type dopant;

forming a first oxide layer over horizontal and vertical surfaces of said silicon mesas and over said source regions;

anisotropically etching said first oxide layer to remove said first oxide layer from all said horizontal surfaces;

forming a second oxide layer over said silicon mesas, said first oxide layer and said source regions, whereby a gate oxide is formed along said vertical surfaces of said silicon mesas, and a tunnel oxide that is thinner than said gate oxide is formed over said source regions;

forming a first conductive layer over said gate oxide, thereby creating said surrounding-gate for said floating memory cell;

forming an interpoly dielectric layer over the vertical surfaces of said first conductive layer, and horizontally over said source regions; and

forming a second conductive layer over said interpoly dielectric layer, which acts as a control gate and word line for said memory cell.

2. The method of claim 1 wherein said

first oxide layer vertical surfaces of said silicon islands and over said is formed by thermal oxidation at a temperature of about 850°

C. for between about 10 to 30 minutes

and said second oxide layer is formed by thermal oxidation at a temperature of between about 800 and 900°

C. for between about 10 to 30 minutes, resulting in a thickness of said gate oxide of between about 120 to 200 Angstroms, and a thickness of said tunnel oxide of between about 60 to 100 Angstroms.

3. The method of claim 1, wherein said silicon mesas are formed to a height of between about 0.3 to 2.0 micrometers.

4. The method of claim 1, wherein said first conductive layer is formed of doped polycrystalline silicon.

5. The method of claim 1, wherein said source and drain regions are doped with arsenic at a concentration of between about 1 E 15 to 8 E 15 atoms/cm².

6. The method of claim 1, wherein said interpoly dielectric layer is formed to a thickness of between about 150 to 300 Angstroms.

7. The method of claim 1, wherein said forming a second oxide layer comprises the steps of:

forming a first layer of silicon oxide, adjacent to said first conductive layer, to a thickness of between about 50 and 150 Angstroms;

forming a layer of silicon nitride, over said first layer of silicon oxide, to a thickness of between about 60 to 200 Angstroms; and

forming a second layer of silicon oxide, over said layer of silicon nitride, to a thickness of between about 30 to 100 Angstroms.

8. The method of claim 1, wherein said second conductive layer is formed of doped polycrystalline silicon, and is formed to a thickness of between about 2000 to 4000 Angstroms.