Method for making fin-shaped stack capacitors on DRAM chips

• US 5,460,999 A
• Filed: 06/06/1994
• Issued: 10/24/1995
• Est. Priority Date: 06/06/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hong, Gary, Hsue, Chen-Chiu
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/254,535
• Time in Patent Office: 505 Days
• Field of Search: 437/47, 437/52, 437/60, 437/919, 257/304-308, 257/311
• US Class Current: 438/397
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multi-layer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a fin-like bottom capacitor electrode. A high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses having the bottom electrode forming therein fin-shaped top capacitor electrode and completing a dynamic random access memory (DRAM) cell. This method also eliminates the need to plasma etch to the source/drain contact during the fabrication of the capacitor, thereby improving reliability and making a more manufacturable process.

Claims

1. A method for fabricating a stacked storage capacitor on a semiconductor substrate having device areas with field effect transistor source/drain areas and word lines formed therein comprising the steps of:

depositing a first polysilicon layer on said substrate and making electrical contact to source/drain area of said device area;

depositing on said first polysilicon layer a multi-layer of two insulator having alternate layers composed of a first insulator and the other layers composed of a second insulator, said insulator having a top surface;

patterning said multilayer over said first polysilicon layer and over and aligned to said source/drain and having vertical sidewalls;

selectively and isotropically etching said first insulator and leaving said second insulator unetched in said sidewall of said multilayer and forming a multiple of fin-shaped recesses in said sidewall;

depositing a second polysilicon layer over and in said multi-layer fin-shaped recesses of said sidewall and forming a fin-shaped polysilicon structure that makes electrical contact to said first polysilicon layer and thereby to said source/drain areas of said device area;

patterning said second and first polysilicon layers leaving portions of said second polysilicon layer over said multilayer and on said top surface of said second insulator and leaving portions of said first polysilicon layer under said multilayer and removing completely said second and first polysilicon layers elsewhere on said substrate thereby forming a bottom capacitor electrode;

depositing a capacitor dielectric layer over said bottom capacitor electrode and forming an interelectrode insulating layer;

depositing a third polysilicon layer over said dielectric layer forming the top capacitor electrode and completing said stacked storage capacitor having a fin-shaped structure.

2. The method of claim 1, wherein said first polysilicon layer is doped with N-type impurities and having a thickness of between about 200 to 1000 Angstroms.

3. The method of claim 1, wherein said multilayer is composed of at least two layers.

4. The method of claim 1, wherein said first insulator and second insulator have different etch rates in the same etchant.

5. The method of claim 4, wherein said first insulator is silicon oxide having a thickness of between about 1000 to 2000 Angstroms and said second insulator is silicon nitride having a thickness between about 300 to 1000 Angstroms.

6. The method of claim 1, wherein said first insulator is deposited first on said first polysilicon layer.

7. The method of claim 1, wherein said second polysilicon layer is doped with N-type impurities and has a thickness of between about 200 to 400 Angstroms.

8. The method of claim 1, wherein said capacitor dielectric is silicon oxide and silicon nitride (ON) having a total thickness of between about 30 to 150 Angstroms.

9. The method of claim 1, wherein said third polysilicon layer is doped with N-type impurities and has a thickness of between about 500 to 2000 Angstroms.

10. The method of claim 1, wherein said bottom capacitor electrode of said storage capacitor makes electrical contact to the source/drain of a field effect transistor in said device area and together comprise a dynamic random access memory cell.

16. The method of claim 1, wherein said first insulator is deposited first over said first polysilicon layer.

11. A method for fabricating a dynamic random access memory (DRAM) cell with a field-effect-transistor (FET) having device source/drains and a storage capacitor formed on and in a semiconductor substrate therein comprising the steps of forming said storage capacitor by:

depositing a first polysilicon layer on said substrate and making contact to said source/drain of said field effect transistor;

depositing on said first polysilicon layer a multilayer of two insulators having alternate layers composed of one insulator, and the other layers composed of a second insulator said second insulator having a top surface;

patterning said multilayer over said first polysilicon layer and over and aligned to said source/drain and having vertical sidewalls;

selectively etching one insulator and leaving said second insulator unetched in said sidewall of said multilayer and forming a multiple of fin-shaped recesses in said sidewall;

depositing a second polysilicon layer over and in said multi-layer fin-shaped recesses of said sidewall and forming a fin-shaped polysilicon structure and making electrical contact to said first polysilicon layer and thereby making electrical contact to said source/drain areas of said fields effect transistor;

patterning said second and first polysilicon layers leaving portions of said second polysilicon layer over said multilayer and on said top surface of said second insulator and leaving portions of said first polysilicon layer under said multilayer and removing completely said second and first polysilicon layers elsewhere on said substrate thereby forming a bottom capacitor electrode of said storage capacitor;

depositing a capacitor dielectric layer over said bottom capacitor electrode and forming an inter-electrode insulating layer;

depositing a third polysilicon layer over said capacitor dielectric layer forming a top capacitor electrode and completing said storage capacitor;

said storage capacitor contacting said source/drain of said field effect transistor and completing said dynamic random access memory cell.

12. The method of claim 11, wherein said first polysilicon layer is doped with N-type impurities and having a thickness of between about 200 to 1000 Angstroms.

13. The method of claim 11, wherein said multilayer is composed of at least two layers.

14. The method of claim 11, wherein the said first insulator and said second insulator having different etch rates in the same etchant.

15. The method of claim 14, wherein said first insulator is silicon oxide having a thickness of between about 1000 to 2000 Angstroms and said second insulator is silicon nitride having a thickness between about 300 to 1000 Angstroms.

17. The method of claim 11, wherein said second polysilicon layer is doped with N-type impurities and has a thickness of between about 200 to 400 Angstroms.

18. The method of claim 11, wherein said capacitor dielectric is silicon oxide and silicon nitride (ON) having a total thickness of between about 30 to 150 Angstroms.

19. The method of claim 11, wherein said third polysilicon layer is doped with N-type impurities and has a thickness of between about 500 to 2000 Angstroms.

20. The method of claim 11, wherein said bottom capacitor electrode of said storage capacitor makes electrical contact to the source/drain of a field effect transistor in said device area and together comprise a dynamic random access memory cell.