Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density

• US 5,461,260 A
• Filed: 08/01/1994
• Issued: 10/24/1995
• Est. Priority Date: 08/01/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Zirkle, Thomas E., Varker, Charles J., Dreyer, Michael L.
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/283,338
• Time in Patent Office: 449 Days
• Field of Search: 257/773, 257/774, 257/775, 257/786, 257/740, 257/767, 257/758, 257/740, 257/765-767, 257/920, 257/923
• US Class Current: 257/773
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow. In a second approach, an interconnect level (50) is formed of a polycrystalline material and connects two points in the semiconductor device using essentially only a plurality of branches (52) each having a linewidth (W) less than the median grain size of the polycrystalline material. In a third approach, an interconnect run (60) consists essentially of a plurality of upper and lower straps (62,64) connected by a plurality of interlevel connectors (66) so that a chain is provided which connects substantially the full length between two points in the semiconductor device.

Claims

1. An interconnect structure for reducing peak localized interconnect current density by distributing current flow around a perimeter of an interlevel connector in a semiconductor device, comprising:

a first interconnect level for connection to a second interconnect level by said interlevel connector, wherein said perimeter of said interlevel connector is disposed at a juncture between said first interconnect level and said interlevel connector; and

at least two fingers protruding from said first interconnect level for connecting to said perimeter of said interlevel connector, wherein said first interconnect level has a first opening proximate to said interlevel connector and disposed between two of said fingers for dividing current flow therebetween.

2. The structure of claim 1 wherein each of said fingers and said first opening are patterned so that current density through each of said fingers is substantially equal in a region proximate to said first interconnect level.

3. The structure of claim 1 wherein each of said fingers has a longitudinal axis intersecting said interlevel connector and separated from each other longitudinal axis of said fingers by a radial rotation of at least about 45 degrees.

4. The structure of claim 1 wherein each of said fingers has a longitudinal axis intersecting said interlevel connector and separated from each other longitudinal axis of said fingers by a radial rotation of at least about 90 degrees.

5. The structure of claim 1 wherein current flow through said first interconnect level is substantially distributed over a radial portion of said perimeter of said interlevel connector of at least about 180 degrees.

6. The structure of claim 1 wherein a resistance path for each of said fingers is substantially equal, said resistance path measured between said perimeter of said interlevel connector and a common point of said first interconnect level distal from said interlevel connector.

7. An interconnect structure for reducing peak localized interconnect current density by distributing current flow around a perimeter of an interlevel connector in a semiconductor device, comprising:

(a) a first interconnect level for connection to a second interconnect level by said interlevel connector, wherein said perimeter of said interlevel connector is disposed at a juncture between said first interconnect level and said interlevel connector; and

(b) at least three fingers protruding from said first interconnect level for connecting to said perimeter of said interlevel connector, wherein;

said first interconnect level has a first opening proximate to said interlevel connector and disposed between two of said fingers for dividing current flow therebetween and has a second opening proximate to said interlevel connector and disposed between two of said fingers for dividing current flow therebetween, one of said fingers disposed between said first opening and said second opening;

said fingers, said first opening, and said second opening are patterned so that current density through each of said fingers in a region proximate to said interlevel connector is substantially equal; and

each of said fingers has a longitudinal axis intersecting said interlevel connector and separated from each other longitudinal axis of said fingers by a radial rotation about a center of said interlevel connector of at least about 45 degrees.

8. The structure of claim 7 wherein said interlevel connector is a via having a closed perimeter comprising at least three edges and each of said fingers connects to one of said edges of said via.

9. The structure of claim 8 wherein said via comprises tungsten and said first interconnect level comprises aluminum.