Semiconductor integrated circuit incorporated with substrate bias control circuit

• US 5,461,338 A
• Filed: 04/16/1993
• Issued: 10/24/1995
• Est. Priority Date: 04/17/1992
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Fukuma, Masao, Hirayama, Takeshi
• Primary Examiner(s): Kincaid, Kristine L.
• Assistant Examiner(s): Riley, Shawn
• Application Number:
  US08/048,662
• Time in Patent Office: 921 Days
• Field of Search: 307/291, 307/296.2, 307/296.3, 307/571, 327/534, 327/538, 327/544
• US Class Current: 327/534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

The semiconductor IC according to this invention comprises an internal circuit including a plurality of transistors formed on a P-type or an N-type substrate (or a well) which carries out a prescribed signal processing operation during the time of operation mode, a standby detection circuit which generates a standby detection signal of active level by detecting standby mode, a bias potential generating circuit which generates a forward bias potential from the substrate (well) of the transistor to the source electrode, and a switching circuit which supplies to the substrate (well) the potential of the source electrode and the bias potential in response to the active level and the inactive level, respectively, of the standby detection signal. At the time of the operation mode, a high speed operation is secured by bringing the transistors to a low threshold voltage by receiving the supply of the bias potential, while at the time of the standby mode, the generation of malfunctions and defective data holding are prevented and the power consumption is saved by raising the threshold voltage of the transistors through a halt of supply of the bias voltage to the substrate (well).

Claims

1. A semiconductor integrated circuit comprising:

an internal circuit including a plurality of transistors formed on a semiconductor substrate area of one conductivity type, said internal circuit carrying out a predetermined signal processing operation in a normal operation mode;

standby detection means for generating a standby detection signal of an active level in a standby mode which is different from said normal operation mode;

means for generating such a bias potential that forwardly biases a junction between said semiconductor substrate area and a source region of each of said plurality of transistors; and

switching means for supplying said semiconductor substrate area with said bias potential in response to an inactive level of said standby detection signal and with a standby potential different from said bias potential in response to said active level of the standby detection signal.

2. A semiconductor integrated circuit as claimed in claim 1, wherein said bias potential is smaller than a flat band voltage between said semiconductor substrate area and said source regions.

3. A semiconductor integrated circuit as claimed in claim 1, wherein said plurality of transistors consist of N-channel transistors and P-channel transistors, and said bias potential generating means generates as said bias potential a first bias potential to be supplied to P-type semiconductor substrate area for said N-channel transistor and a second bias potential to be supplied to N-type semiconductor substrate area for said P-channel transistor.

4. A semiconductor integrated circuit as claimed in claim 1, further comprising means for stopping supply of power voltage to said bias potential generating means in response to the active level of said standby mode detection signal.

5. A semiconductor integrated circuit comprising an internal circuit having a normal operation mode and a standby mode, said internal circuit including a plurality of insulated gate field effect transistors each having source and drain regions formed in a substrate area, said source region being supplied with a power voltage, and a substrate bias control circuit coupled to said substrate area and supplying said substrate area with said power voltage in said standby mode and with a bias voltage in said normal operation mode, said bias voltage being different from said power voltage.

6. The integrated circuit as claimed in claim 5, wherein said substrate bias control circuit includes a voltage generator generating said bias voltage at an output node thereof, a voltage line supplied with said power voltage, and a switching circuit forming an electrical path between said substrate area and said output node of said voltage generator in said normal operation mode and between said substrate area and said voltage line in said standby mode.

7. The integrated circuit as claimed in claim 5, wherein said source region is of an N-type and said substrate area is of a P-type and is biased more positively than said source region by said bias voltage in said normal operation mode.

8. The integrated circuit as claimed in claim 5, wherein said source region is of a P-type and said substrate area is of an N-type and biased more negatively than said source region by said bias voltage in said normal operation mode.