Semiconductor memory comprising a memory cell without a transistor

• US 5,463,235 A
• Filed: 07/25/1994
• Issued: 10/31/1995
• Est. Priority Date: 07/26/1993
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ishii, Tatsuya
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/279,598
• Time in Patent Office: 463 Days
• Field of Search: 257/300, 257/306, 257/311, 257/317, 257/318, 257/319, 257/320, 257/321, 257/535, 365/180, 365/184, 365/185
• US Class Current: 257/300
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory includes a laminated structure including a first word line in a p-type silicon substrate, a first silicon oxide film on the word line, a bit line, a tunnel oxide film, a storage node of polycrystalline silicon containing impurities, a second silicon oxide film, and a second word line of polycrystalline silicon, wherein the dielectric constant or area of the tunnel oxide film is smaller than the dielectric constant or area of the first silicon oxide film and smaller than the dielectric constant or the area of the second silicon oxide film. With this arrangement, the memory cell structure can be extremely simple. It is possible to reduce the number of production steps and, therefore, it is also possible to improve production yield. The present invention provides a high-density, high-performance, and low cost semiconductor memory.

Claims

1. A semiconductor memory comprising a memory cell, said memory cell being free of transistors and comprising:

a laminated structure including a first word line, a first dielectric film having a first area and a first dielectric constant and disposed on said first word line, a bit line disposed on said first dielectric film, a second dielectric film having a second area and a second dielectric constant and disposed on said bit line, an information charge storage layer disposed on said second dielectric film, a third dielectric film having a third area and a third dielectric constant and disposed on said information charge storage layer, and a second word line disposed on said third dielectric film, wherein at least one of the second area and the second dielectric constant is smaller than the first area and the first dielectric constant, respectively, and the third area and the third dielectric constant, respectively.

4. The semiconductor memory according to claim 1 wherein said first and second word lines are arranged in an X-direction and said bit line is arranged in a Y-direction, a memory cell being disposed at every intersection between said bit line and said first and second word lines in a folded bit line scheme.

2. A semiconductor memory comprising a memory cell, said memory cell being free of transistors and comprising:

a silicon substrate having a primary surface;

a first word line comprising a doped region in said silicon substrate at the primary surface of said silicon substrate;

a first silicon oxide film having a dielectric constant and an area and disposed on said first word line;

a bit line comprising polycrystalline silicon containing impurities disposed on said first silicon oxide film;

a tunnel oxide film having a dielectric constant and an area and disposed on said bit line;

an information charge storage layer comprising polycrystalline silicon containing impurities disposed on said tunnel oxide film;

a second silicon oxide film having a dielectric constant and an area and disposed on said information charge storage layer, at least one of the dielectric constant and the area of said tunnel oxide film being smaller than the dielectric constant and the area of said first silicon oxide film, respectively, and than the dielectric constant and the area of said second silicon oxide film, respectively; and

a second word line comprising polycrystalline silicon containing impurities disposed on said second silicon oxide film.

3. A semiconductor memory comprising a memory cell, said memory cell being free of transistors and comprising:

a silicon substrate having a primary surface;

a second word line comprising a doped region in said silicon substrate at the primary surface of said silicon substrate;

a second silicon oxide film having a dielectric constant and an area and disposed on said second word line;

an information charge storage layer comprising polycrystalline silicon containing impurities disposed on said second silicon oxide film;

a tunnel oxide film having a dielectric constant and an area disposed on said information storage layer;

a bit line comprising polycrystalline silicon containing impurities disposed on said tunnel oxide film;

a first silicon oxide film having a dielectric constant and an area and disposed on said bit line, at least one of the dielectric constant and the area of said tunnel oxide film being smaller than the dielectric constant and the area of said first silicon oxide film and than the dielectric constant and the area of said second silicon oxide film; and

a first word line comprising polycrystalline silicon containing impurities disposed on said first silicon oxide film.