Large scale high density semiconductor apparatus

• US 5,463,246 A
• Filed: 05/03/1994
• Issued: 10/31/1995
• Est. Priority Date: 12/29/1988
• Status: Expired due to Term

• Current Assignee: Sharp Electronics Corporation (Hon Hai Precision Industry Co., Ltd.), Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Matsunami, Mitsuo
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/237,324
• Time in Patent Office: 546 Days
• Field of Search: 357/55, 357/68, 357/69, 257/507, 257/621, 257/624, 257/698, 257/774, 257/783, 437/203, 437/208, 437/228, 437/245
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A large scale semiconductor apparatus is provided which includes at least one semiconductor chip having electrodes. The semiconductor chip is bonded on an electrically insulating circuit substrate on which electrically conductive interconnection films are separately formed, and a plurality of through holes are formed in the semiconductor chip so as to pierce the semiconductor chip in the direction of the thickness thereof. Electrically conductive bodies are formed in the through holes, respectively, wherein each of the conductive bodies electrically connects a predetermined electrode of the semiconductor chip to a predetermined interconnection film formed on the circuit substrate.

Claims

1. A method for forming a semiconductor apparatus, comprising the steps of:

(a) separately forming a plurality of electrically conductive interconnection films of a predetermined pattern on an electrically insulating circuit substrate;

(b) bonding at least one semiconductor chip having a plurality of electrodes through an adhesive layer on said circuit substrate and said interconnection films;

(c) forming a plurality of through holes in said semiconductor chip which pierce said semiconductor chip in the direction of thickness thereof; and

(d) forming a plurality of electrically conductive bodies in each of said through holes respectively, each of said plurality of electrically conductive bodies electrically connecting a predetermined one of said electrodes of said semiconductor chip to a predetermined one of said interconnection films formed on said circuit substrate,

wherein each of said plurality of electrically conductive bodies is electrically connected directly to said predetermined one of said interconnection films on the bottom plane of each of said through holes.

2. The method as claimed in claim 1, wherein each of said conductive bodies is disposed in each of said through holes at said step (d).

5. The method as claimed in claim 1, wherein said step (b) comprises the step of bonding at least one of said electrodes of said semiconductor chip to said interconnection films through an adhesive layer and subsequently etching to remove a portion of said adhesive layer located beneath said through holes.

10. The method of claim 1, wherein in step (d) each one of the plurality of electrically conductive bodies are electrically directly connected to said predetermined one of said interconnection films by direct physical contact of each one of the plurality of electrically conductive bodies to said predetermined one of said interconnection films.

3. A method for forming a semiconductor apparatus, comprising the steps of:

(a) separately forming a plurality of electrically conductive interconnection films of a first predetermined pattern on an electrically insulating circuit substrate;

(b) bonding at least one semiconductor chip having a plurality of electrodes through an adhesive layer on said circuit substrate and said interconnection films so that a top surface and inclined side surfaces of each of said semiconductor chips are exposed; and

(c) separately forming a plurality of first electrically conductive films of a second predetermined pattern on said top surface and said inclined side surface of each of said semiconductor chips and a top surface of said circuit substrate, each of said plurality of first electrically conductive films electrically connecting a predetermined one of said electrodes of said semiconductor chip to a predetermined one of said interconnection films formed on said circuit substrate.

4. The method as claimed in claim 3, further comprising the steps of:

(d) bonding first and second semiconductor chips through each adhesive layer on said circuit substrate so that respective top surface and respective inclined side surfaces of said first and second semiconductor chips are exposed are adjacent to each other; and

(e) forming at least one second electrically conductive film on respective top surfaces and respective side surfaces of said first semiconductor chip and said second semiconductor chip and a top surface of said circuit substrate for electrically connecting a predetermined one of said electrodes of said first semiconductor chip to a predetermined one of said electrodes of a second semiconductor chip.

6. A semiconductor apparatus comprising:

an electrically insulating circuit substrate;

a plurality of electrically conductive interconnection film of a predetermined pattern separately formed on said circuit substrate;

at least one semiconductor chip having a plurality of electrodes, said semiconductor chip being bonded through an adhesive layer on said circuit substrate and said interconnection films;

a plurality of through holes formed in said semiconductor chip so as to pierce said semiconductor chip in the direction of the thickness thereof; and

a plurality of electrically conductive bodies formed in each of said through holes, respectively, each of said conductive bodies electrically connecting a predetermined one of said electrodes of said semiconductor chip to a predetermined one of said interconnection films formed on said circuit substrate,

wherein each of said conductive bodies is electrically connected directly to said predetermined one of said interconnection films formed on said circuit substrate on the bottom plane of each of said plurality of through holes and each of said conductive bodies is disposed in each of said through holes.

7. A semiconductor apparatus comprising:

an electrically insulating circuit substrate;

a plurality of electrically conductive interconnection films of a first predetermined pattern separately formed on said circuit substrate;

at least one semiconductor chip having a top surface and inclined side surfaces and a plurality of electrodes, said semiconductor chip being bonded through an adhesive layer on said circuit substrate and said interconnection films so that said top surface and said inclined surfaces of each of said semiconductor chips are exposed; and

a plurality of first electrically conductive films of a second predetermined pattern separately formed on said top surface and said respective inclined side surfaces of each of said semiconductor chips, each of said first conductive films electrically connecting a predetermined one of said electrodes of said semiconductor chip to a predetermined one of said interconnection films formed on said circuit substrate, by leading said first conductive film from said one predetermined electrode through said top surface and said inclined surface of each of said semiconductor chips to said predetermined one of said interconnection films of said circuit substrate.

8. A semiconductor apparatus comprising:

an electrically insulating circuit substrate;

electrically conductive interconnection films of a first predetermined pattern separately formed on said circuit substrate;

a plurality of semiconductor chips bonded through respective adhesive layers so as to be stacked on said circuit substrate, each of said plurality of semiconductor chips having a top surface, inclined side surfaces and a plurality of electrodes; and

electrical connection means of a second predetermined pattern formed on said top surface and said inclined side surface of each of said semiconductor chips, said electrical connection means electrically connecting a predetermined one of said electrodes of each of said semiconductor chips to a predetermined one of interconnection films formed on another one of said semiconductor chips.

9. The semiconductor apparatus as claimed in claim 8, further comprising:

a plurality of through holes formed in a predetermined one of said semiconductor chips so as to pierce said predetermined one of said semiconductor chips in the direction of the thickness thereof; and

a plurality of electrically conductive bodies formed in each of said through holes, respectively, each of said conductive bodies electrically connecting a predetermined one of said electrodes of said semiconductor chip to a predetermined one of interconnection films formed on another one of said semiconductor chips,

wherein each of said conductive bodies is electrically connected directly to said predetermined one of said interconnection films formed on another one of said semiconductor chips, on the bottom plane of each of said plurality of through holes and each of said conductive bodies is disposed in each of said through holes.