Semiconductor device having a plurality of chips

• US 5,463,253 A
• Filed: 05/20/1994
• Issued: 10/31/1995
• Est. Priority Date: 03/15/1990
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kasai, Junichi, Honda, Toshiyuki, Sato, Hirotaka, Aoki, Tsuyoshi, Waki, Masaki
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/246,567
• Time in Patent Office: 529 Days
• Field of Search: 257/685, 257/686, 257/723, 257/666, 257/777, 257/723, 257/724, 257/725, 257/783, 257/787
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor device includes lead frames (21) respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces, a first semiconductor chip (22) arranged on first main surface sides of the lead frames, first tape leads (23) electrically connecting the first main surfaces of the lead frames to the first semiconductor chip, a second semiconductor chip (24) arranged on second main surface sides of the lead frames, and second tape leads (25) electrically connecting the second main surfaces of the lead frames to the second semiconductor.

Claims

1. A semiconductor device comprising:

lead frames respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces;

a first semiconductor chip;

first tape leads electrically connecting the first main surfaces of the lead frames to the first semiconductor chip;

a second semiconductor chip spaced apart from the first semiconductor chip;

second tape leads electrically connecting the second main surfaces of the lead frames to the second semiconductor chip; and

an electrically conductive adhesive layer which is provided between the first semiconductor chip and the second semiconductor chip and which fixes the first semiconductor chip and the second semiconductor chip to each other;

the first semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface;

the second semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor chip; and

the second surface of the first semiconductor chip is opposed to the second surface of the second semiconductor chip.

2. A semiconductor device as claimed in claim 1, wherein:

the first semiconductor chip comprises a plurality of terminals on the first surface thereof;

the second semiconductor chip comprises a plurality of terminals on the first surface thereof;

the first tape leads are connected to the plurality of terminals formed on the first surface of the first semiconductor chip; and

the second tape leads are connected to the plurality of terminals formed on the first surface of the second semiconductor chip.

3. A semiconductor device as claimed in claim 2, wherein the first tape leads and the second tape leads have respective bent portions which make the first semiconductor chip and the second semiconductor chip spaced apart from each other.

4. A semiconductor device as claimed in claim 3, wherein the first tape leads substantially extend in parallel to the second tape leads.

5. A semiconductor device as claimed in claim 1, wherein:

the first semiconductor chip comprises a plurality of terminals;

the second semiconductor chip comprises a plurality of terminals; and

the plurality of terminals of the first semiconductor chip are a mirror image of the plurality of terminals of the second semiconductor chip.

6. A semiconductor device as claimed in claim 1, wherein:

the lead frames include a chip select lead frame receiving a chip select signal output by an external circuit;

the first semiconductor chip comprises first chip select means, connected to the chip select lead frame, for activating the first semiconductor chip when the chip select signal has a first value; and

the second semiconductor chip comprises second chip select means, connected to the chip select lead frame, for activating the second semiconductor chip when the chip select signal has a second value.

7. A semiconductor device as claimed in claim 1, wherein:

the first semiconductor chip comprises an internal circuit;

the second semiconductor chip comprises an internal circuit; and

the internal circuit of the first semiconductor chip has a mirror image pattern with that of the internal circuit of the second semiconductor chip.

8. A semiconductor device as claimed in claim 1, wherein:

the first semiconductor chip comprises an internal circuit;

the second semiconductor chip comprises an internal circuit; and

the internal circuit of the first semiconductor chip has a pattern asymmetrical with that of the internal circuit of the second semiconductor chip°

9. A semiconductor device as claimed in claim 1, wherein:

the first semiconductor chip is a semiconductor memory; and

the second semiconductor chip is a semiconductor memory.

10. A semiconductor device as claimed in claim 1, wherein the lead frames comprise plating layers respectively formed on the first main surfaces and the second main surfaces.

11. A semiconductor device comprising:

lead frames respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces;

a first semiconductor chip;

first tape leads electrically connecting the first main surfaces of the lead frames to the first semiconductor chip;

a second semiconductor chip;

second tape leads electrically connecting the second main surfaces of the lead frames to the second semiconductor chip; and

a molded resin layer which packages the first semiconductor chip and the second semiconductor chip;

the first semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface;

the second semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor chip;

the second surface of the first semiconductor chip is opposed to the second surface of the second semiconductor chip; and

substantially only the molded resin layer fills a space between the second surface of the first semiconductor chip and the second surface of the second semiconductor chip.

12. A semiconductor device as claimed in claim 11, wherein:

the first semiconductor chip comprises a plurality of terminals on the first surface thereof;

the second semiconductor chip comprises a plurality of terminals on the first surface thereof;

the first tape leads are connected to the plurality of terminals formed on the first surface of the first semiconductor chip; and

the second tape leads are connected to the plurality of terminals formed on the first surface of the second semiconductor chip.

13. A semiconductor device as claimed in claim 12, wherein the first tape leads and the second tape leads have respective bent portions which make the first semiconductor chip and the second semiconductor chip spaced apart from each other.

14. A semiconductor device as claimed in claim 13, wherein the first tape leads substantially extend in parallel to the second tape leads.

15. A semiconductor device as claimed in claim 11, wherein:

the first semiconductor chip comprises a plurality of terminals;

the second semiconductor chip comprises a plurality of terminals; and

the plurality of terminals of the first semiconductor chip are a mirror image of the plurality of terminals of the second semiconductor chip.

16. A semiconductor device as claimed in claim 11, wherein:

the lead frames includes a chip select lead frame receiving a chip select signal output by an external circuit;

the first semiconductor chip comprises first chip select means, connected to the chip select lead frame, for activating the first semiconductor chip when the chip select signal has a first value; and

the second semiconductor chip comprises second chip select means, connected to the chip select lead frame, for activating the second semiconductor chip when the chip select signal has a second value.

17. A semiconductor device as claimed in claim 11, wherein:

the first semiconductor chip comprises an internal circuit;

the second semiconductor chip comprises an internal circuit; and

the internal circuit of the first semiconductor chip has a mirror image pattern with that of the internal circuit of the second semiconductor chip.

18. A semiconductor device as claimed in claim 11, wherein:

the first semiconductor chip comprises an internal circuit;

the second semiconductor chip comprises an internal circuit; and

the internal circuit of the first semiconductor chip has a pattern asymmetrical with that of the internal circuit of the second semiconductor chip.

19. A semiconductor device as claimed in claim 11, wherein:

the first semiconductor chip is a semiconductor memory; and

the second semiconductor chip is a semiconductor memory.

20. A semiconductor device as claimed in claim 11, wherein the lead frames comprise plating layers respectively formed on the first main surfaces and the second main surfaces.

21. A semiconductor device comprising:

lead frames respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces;

a first semiconductor chip;

first tape leads electrically connecting the first main surfaces of the lead frames to the first semiconductor chip;

a second semiconductor chip; and

second tape leads electrically connecting the second main surfaces of the lead frames to the second semiconductor chip;

the first semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface;

the second semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor ship; and

the second surface of the first semiconductor chip is opposed to and in direct contact with the second surface of the second semiconductor chip.

22. A semiconductor device as claimed in claim 21, wherein:

the first semiconductor chip comprises a plurality of terminals on the first surface thereof;

the second semiconductor chip comprises a plurality of terminals on the first surface thereof;

the first tape leads are connected to the plurality of terminals formed on the first surface of the first semiconductor chip; and

the second tape leads are connected to the plurality of terminals formed on the first surface of the second semiconductor chip.

23. A semiconductor device as claimed in claim 22, wherein the first tape leads and the second tape leads have respective bent portions which make the first semiconductor chip and the second semiconductor chip spaced apart from each other.

24. A semiconductor device as claimed in claim 23, wherein the first tape leads substantially extend in parallel to the second tape leads.

25. A semiconductor device as claimed in claim 21, wherein:

the first semiconductor chip comprises a plurality of terminals;

the second semiconductor chip comprises a plurality of terminals; and

the plurality of terminals of the first semiconductor chip are a mirror image of the plurality of terminals of the second semiconductor chip.

26. A semiconductor device as claimed in claim 21, wherein:

the lead frames includes a chip select lead frame receiving a chip select signal output by an external circuit;

the first semiconductor chip comprises first chip select means, connected to the chip select lead frame, for activating the first semiconductor chip when the chip select signal has a first value; and

the second semiconductor chip comprises second chip select means, connected to the chip select lead frame, for activating the second semiconductor chip when the chip select signal has a second value.

27. A semiconductor device as claimed in claim 21, wherein:

the first semiconductor chip comprises an internal circuit;

the second semiconductor chip comprises an internal circuit; and

the internal circuit of the first semiconductor chip has a mirror image pattern with that of the internal circuit of the second semiconductor chip.

28. A semiconductor device as claimed in claim 21, wherein:

the first semiconductor chip comprises an internal circuit;

the second semiconductor chip comprises an internal circuit; and

the internal circuit of the first semiconductor chip has a pattern asymmetrical with that of the internal circuit of the second semiconductor chip.

29. A semiconductor device as claimed in claim 21, wherein:

the first semiconductor chip is a semiconductor memory; and

the second semiconductor chip is a semiconductor memory.

30. A semiconductor device as claimed in claim 21, wherein the lead frames comprise plating layers respectively formed on the first main surfaces and the second main surfaces.

31. A semiconductor device comprising:

first and second semiconductor chips forming a first pair;

third and fourth semiconductor chips forming a second pair located in a position opposite to the first pair;

a plurality of lead frames having first portions and second portions spaced apart from the first portions, the first and second portions having first main surfaces and second main surfaces opposite to the first main surfaces, the first pair being located on the side of the first portions of the lead frames, the second pair being located on the side of the second portions of the lead frames, bonding being able to be performed on the first and second main surfaces, the plurality of lead frames extending into the semiconductor device, but not extending substantially between the first pair and not extending substantially between the second pair;

first tape leads electrically connecting the first main surfaces of the first portions of the lead frames to the first semiconductor chip;

second tape leads electrically connecting the second main surfaces of the first portions of the lead frames to the second semiconductor chip;

third tape leads electrically connecting the first main surfaces of the second portions of the lead frames to the third semiconductor chip;

fourth tape leads electrically connecting the second main surfaces of the second portions of the lead frames to the fourth semiconductor chip; and

a molded resin layer packaging the first through fourth semiconductor chips, the molded resin layer filling a space between the first and second semiconductor chips and a space between the third and fourth semiconductor chips.

32. A semiconductor device as claimed in claim 31, wherein:

the first semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface;

the second semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor chip;

the third semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the third semiconductor chip;

the fourth semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the fourth semiconductor chip;

the second surface of the third semiconductor chip is opposed to the second surface of the fourth semiconductor chip; and

the first surface of the second semiconductor chip is opposed to the first surface of the third semiconductor chip.

33. A semiconductor device as claimed in claim 31, wherein:

each of the first, second, third and fourth semiconductor chips has terminals arranged in a line at a central portion of a surface thereof; and

the first, second, third and fourth tape leads are connected to the terminals of the first, second, third and fourth semiconductor chips, respectively.

34. A semiconductor device as claimed in claim 31, wherein the semiconductor device comprises a molded resin layer which packages the first, second, third and fourth semiconductor chips.

35. A semiconductor device as claimed in claim 31, wherein:

the plurality of lead frames include at least one chip select lead frame receiving a chip select signal output by an external circuit;

the first semiconductor chip comprises first chip select means, connected to the chip select lead frame, for activating the first semiconductor chip when the chip select signal has a first value;

the second semiconductor chip comprises second chip select means, connected to the chip select lead frame, for activating the second semiconductor chip when the chip select signal has a second value;

the third semiconductor chip comprises third chip select means, connected to the chip select lead frame, for activating the third semiconductor chip when the chip select signal has a third value; and

the fourth semiconductor chip comprises fourth chip select means, connected to the chip select lead frame, for activating the fourth semiconductor chip when the chip select signal has a fourth value.

36. A semiconductor device as claimed in claim 31, wherein:

the first semiconductor chip is a semiconductor memory;

the second semiconductor chip is a semiconductor memory;

the third semiconductor chip is a semiconductor memory; and

the fourth semiconductor chip is a semiconductor memory.

37. A semiconductor device as claimed in claim 31, wherein said semiconductor device comprises:

a first adhesive layer which is provided between the first and second semiconductor chips and fixes the first and second semiconductor chips to each other; and

a second adhesive layer which is provided between the third and fourth semiconductor chips and fixes the third and fourth semiconductor chips to each other.

38. A semiconductor device comprising:

first and second semiconductor chips forming a first pair;

third and fourth semiconductor chips forming a second pair;

the distance between the first and fourth semiconductor chips being..greater than the distance between the first and third semiconductor chips and the distance between the first and third semiconductor chips being greater than the distance between the first and second semiconductor chips;

lead frames having first and second surfaces, bonding being able to be performed on the first and second surfaces;

first tape leads electrically connecting the first and second semiconductor chips to the first surfaces of the lead frames; and

second tape leads electrically connecting the third and fourth semiconductor chips to the second surfaces of the lead frames.

39. A semiconductor chip as claimed in claim 38, wherein each of the first, second, third and fourth semiconductor chip is a semiconductor memory.

40. A semiconductor chip as claimed in claim 38, further comprising a molded resin layer which packages the first, second, third and fourth semiconductor chips.

41. A semiconductor device as claimed in claim 38, wherein:

the first semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface;

the second semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor chip;

the first surface of the first semiconductor chip including the internal circuit thereof is opposed to the first surface of the second semiconductor chip;

the third semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor chip;

the fourth semiconductor chip has a first surface including an internal circuit, and a second surface opposite to the first surface of the second semiconductor chip; and

the first surface of the third semiconductor chip is opposed to the first surface of the fourth semiconductor chip.

42. A semiconductor device as claimed in claim 41, wherein the second surface of the second semiconductor chip is in contact with the second surface of the third semiconductor chip.

43. A semiconductor device as claimed in claim 41, wherein the second surface of the second semiconductor chip is spaced apart from the second surface of the third semiconductor chip.

44. A semiconductor device as claimed in claim 38, wherein:

the first tape leads have first and second tape portions which overlap with each other;

the first tape portions are connected to the first semiconductor chip, and the second tape portions connect the second semiconductor chip to the first main surfaces of the lead frames;

the second tape leads have first and second tape portions which overlap with each other;

the first tape portions of the second tape leads connect the third semiconductor chip to the second main surfaces of the lead frames; and

the second tape portions of the second tape leads are connected to the fourth semiconductor chip.

45. A semiconductor device as claimed in claim 44, wherein the first and second tape portions of each of the first and second tape leads are in close contact with each other and electrically connected to each other.

46. A semiconductor device as claimed in claim 44, wherein:

the first and second tape portions of the first tape leads are bonded to the first main surfaces of the lead frames at first and second positions thereon; and

the first and second tape portions of the second tape leads are bonded to the second main surfaces of the lead frames at first and second positions thereon.

47. A semiconductor chip as claimed in claim 46, wherein the first and second positions on the first main surface are opposed to the first and second positions on the second main surface.

48. A semiconductor device comprising:

first and second semiconductor chips forming a first pair;

third and fourth semiconductor chips forming a second pair;

lead frames having first and second surfaces, bonding being able to be performed on the first and second surfaces;

first tape leads electrically connecting the first and second semiconductor chips to the first surfaces of the lead frames; and

second tape leads electrically connecting the third and fourth semiconductor chips to the second surfaces of the lead frames;

at least one chip select tape lead is included in the first and second tape leads;

the chip select tape lead has an insulating film interposed between a first tape portion and a second tape portion thereof;

said insulating film has a contact hole; and

the first and second tape portions of the chip select tape lead are electrically connected to each other through the contact hole.

49. A semiconductor device comprising:

first and second semiconductor chips forming a first pair;

third and fourth semiconductor chips forming a second pair;

lead frames having first and second surfaces, bonding being able to be performed on the first and second surfaces;

first tape leads electrically connecting the first and second semiconductor chips to the first surfaces of the lead frames; and

second tape leads electrically connecting the third and fourth semiconductor chips to the second surfaces of the lead frames;

at least one chip select tape lead is included in the first and second tape leads;

the chip select tape lead has an insulating film interposed between a first tape portion and a second tape portion thereof;

said insulating film has a contact hole;

one of the first and second tape portions of the chip select tape lead has a cut-out portion through which the contract hole is exposed; and

the first and ;

second tape portions of the chip select tape lead are electrically insulated from each other by the insulating film.

50. A semiconductor device comprising:

first and second semiconductor chips forming a first pair;

third and fourth semiconductor chips forming a second pair;

lead frames having first and second surfaces, bonding being able to be performed on the first and second surfaces;

first tape leads electrically connecting the first and second semiconductor chips to the first surfaces of the lead frames;

second tape leads electrically connecting the third and fourth semiconductor chips to the second surfaces of the lead frames;

fifth, sixth, seventh and eighth tape leads for use in chip selection; and

first and second chip select leads of the lead frames for chip select;

the fifth tape lead electrically connects the first and second semiconductor chips to the first chip select lead;

the sixth tape lead electrically connects one of the first and second semiconductor chips to the second chip select lead;

the seventh tape lead electrically connects the third and fourth semiconductor chips to the first chip select lead; and

the eighth tape lead electrically connects one of the third and fourth semiconductor chips to the second chip select lead.

51. A semiconductor device as claimed in claim 50, wherein:

the first chip select lead has a first main surface bonded to the fifth tape lead, and a second main surface opposite to the first main surface of the first chip select lead and bonded to the seventh tape lead; and

the second chip select lead has a third main surface bonded to the sixth tape lead, and a fourth main surface opposite to the third main surface and bonded to the eighth tape lead.

52. A semiconductor device comprising:

first and second semiconductor chips forming a first pair;

third and fourth semiconductor chips forming a second pair located in a position opposite to the first pair;

a plurality of lead frames having first portions and second portions spaced apart from the first portions, the first and second portions having first main surfaces and second main surfaces opposite to the first main surfaces, the first pair being located on the side of the first portions of the lead frames, the second pair being located on the side of the second portions of the lead frames, bonding being able to be performed on the first and second main surfaces, the plurality of lead frames extending into the semiconductor device, but not extending substantially between the first pair and not extending substantially between the second pair;

first tape leads electrically connecting the first main surfaces of the first portions of the lead frames to the first semiconductor chip;

second tape leads electrically connecting the second main surfaces of the first portions of the lead frames to the second semiconductor chip;

third tape leads electrically connecting the first main surfaces of the second portions of the lead frames to the third semiconductor chip;

fourth tape leads electrically connecting the second main surfaces of the second portions of the lead frames to the fourth semiconductor chip;

a first electrically conductive adhesive layer provided between the first and second semiconductor chips and adhering the first and second semiconductor chips to one another; and

a second electrically conductive adhesive layer provided between the third and fourth semiconductor chips and adhering the third and fourth semiconductor chips to one another.-