Semi-flash type A/D converter employing a correction encoder for eliminating errors in the output signals due to noise, and a corresponding method therefor

• US 5,463,395 A
• Filed: 09/28/1993
• Issued: 10/31/1995
• Est. Priority Date: 09/28/1992
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Sawai, Yasunori
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/127,373
• Time in Patent Office: 763 Days
• Field of Search: 341/94, 341/156, 341/158, 341/159, 341/160
• US Class Current: 341/156
• CPC Class Codes: H03M 1/0809 of bubble errors, i.e. irregularities in thermometer codes
• CPC Class Codes: H03M 1/144 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array

Abstract

A semi-flash type analog/digital converter for eliminating errors in its output signals which are caused by noise. The analog/digital converter includes a D/A converter for outputting a plurality of analog signals which are produced based on a plurality of input signals. A plurality of comparators compare the voltage of an analog input signal, provided via a sample and hold circuit, with the analog signals output from the D/A converter. The output from the comparators are supplied to two latches, which further provide the outputs to a plurality of encoders. One of the encoders encodes the signals provided by one of the latches and outputs signals representative of high order bits of a digital signal. A second encoder, which encodes output signals provided by the other latch, is a correction encoder. The correction encoder corrects the signals provided by the latch if it determines that any of the signals are in error, and outputs signals representing the lower order bits of a digital output signal. The correction encoder includes either a priority control circuit or an adder circuit which performs the correction.

Claims

1. A semi-flash type analog/digital converter comprising:

digital/analog conversion means for outputting a plurality of analog signals having voltages corresponding to output data of said analog/digital converter;

a plurality of comparators, each for comparing a voltage of an associated one of said analog signals output from said digital/analog conversion means with a voltage of an analog signal to be converted into digital data;

encoding means, connected to said digital/analog conversion means and said comparators, for encoding output signals of said plurality of comparators to generate the output data of said analog/digital converter, said encoding means including correction encoding means for correcting said output signals of said plurality of comparators when said output signals are in error, and encoding said corrected signal, said correction encoding means comprising an adder circuit for adding input signals, which are based on said output signals of a predetermined number of said comparators, to provide a predetermined output signal; and

analog signal input means for receiving said analog signal to be converted into said digital data and supplying said analog signal to said plurality of comparators.

2. The semi-flash type analog/digital converter according to claim 1, wherein said correction encoding means comprises means for judging that a most significant digit signal of those signals from said comparators which have a first logic level has a second logic level and signals at lower digits than said most significant digit signal have said first logic level, and encoding said signals.

3. A semi-flash type analog/digital converter, comprising:

digital/analog conversion means for outputting a predetermined first group of analog signals for producing predetermined upper bits of an analog/digital conversion result, and a second group of analog signals which are to produce predetermined lower bits of said analog/digital conversion result and are associated to said predetermined upper bits;

a selector for selecting one of said first group of analog signals and said second group of analog signals, and supplying said selected group of analog signals;

.

a plurality of comparators for each comparing a voltage of an associated one of said output signals of said selector with a voltage of an analog signal to be converted into digital data;

first encoding means for encoding output signals of said plurality of comparators which are associated with said first group of analog signals to acquire said predetermined upper bits of said analog/digital conversion result, and supplying signals corresponding to said predetermined upper bits to said digital/analog conversion means; and

second encoding means for encoding output signals of said plurality of comparators which are associated with said second group of analog signals to acquire said predetermined lower bits of said analog/digital conversion result, said second encoding means having means for correcting any of said output signals of said plurality of comparators when that output signal is in error, and encoding said corrected signal;

wherein said correction encoding means comprises an adder circuit for adding input signals to acquire a predetermined output signal.

4. The semi-flash type analog/digital converter according to claim 3, wherein said correction encoding means comprises means for judging that a most significant bit signal of those signals from said comparators which have a first logic level has a second logic level and that those signals at lower positions than said most significant bit signal have said first logic level, and encoding said signals.

5. A semi-flash type A/D converting method, comprising:

a step of sampling an analog signal to be converted into a digital signal;

a step of producing a first group of analog signals having predetermined mutually different voltages;

a first comparison step of comparing each of said first group of analog signals with said analog signal sampled in said sampling step and outputting signals corresponding to comparison results;

a first encoding step of encoding signals output in said first comparison step;

a step of producing a second group of analog signals having mutually different voltages in association with digital data acquired in said first encoding step;

a second comparison step of comparing each of said second group of analog signals with said analog signal sampled in said sampling step and outputting signals corresponding to comparison results;

a second encoding step of encoding signals output in said second comparison step, said second encoding step including a step of correcting any of said output signals of said second comparison step when that output signal is in error, and encoding said corrected signal; and

a step of linking digital signals acquired in said first and second encoding steps to acquire a conversion result;

wherein said second encoding step includes an adding step for adding outputs signals acquired in said comparison steps to acquire a predetermined output signal.

6. A semi-flash type A/D converting method, comprising:

a step of sampling an analog signal to be converted into a digital signal;

a step of producing a first group of analog signals having predetermined mutually different voltages;

a first comparison step of comparing each of said first group of analog signals with said analog signal sampled in said sampling step and outputting signals corresponding to comparison results;

a first encoding step of encoding signals output in said first comparison step;

a step of producing a second group of analog signals having mutually different voltages in association with digital data acquired in said first encoding step;

a second comparison step of comparing each of said second group of analog signals with said analog signal sampled in said sampling step and outputting signals corresponding to comparison results;

a second encoding step of encoding signals output in said second comparison step, said second encoding step including a step of correcting any of said output signals of said second comparison step when that output signal is in error, and encoding said corrected signal; and

a step of linking digital signals acquired in said first and second encoding Steps to acquire a conversion result;

wherein said second encoding step includes a step of judging that a most significant bit signal of those signals acquired in said second comparison step which have a first logic level has a second logic level and that signals at lower positions than said most significant bit signal have said first logic level, and encoding said signals.