Design automation method for digital electronic circuits

• US 5,463,562 A
• Filed: 12/20/1994
• Issued: 10/31/1995
• Est. Priority Date: 03/03/1994
• Status: Expired due to Fees

• Current Assignee: International Computers Limited (Fujitsu Limited)
• Original Assignee: International Computers Limited (Fujitsu Limited)
• Inventors: Theobald, Leonard
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/359,519
• Time in Patent Office: 315 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/176, 364/578, 395/500, 371/22.6, 371/22.5, 371/22.1, 371/22.2, 371/22.3
• US Class Current: 716/105
• CPC Class Codes: G01R 31/318392 for sequential circuits G01R31/318544 takes precedence

Abstract

A design automation method for digital electronic circuits, including the steps of synthesizing a circuit including at least one logic tree, and then automatically partitioning the logic tree. The automatic partitioning process involves first identifying a set of driving bits for each of a set of points within the tree, ie the tree inputs that affect each of those points. Then, for each of those points, the partitioning process identifies a set of splittable input bits that can be isolated by insertion of a fence register at that point, and identifies which of those points are possible fence points, having more than one splittable input bit. Finally, the partitioning process selects a sub-set of the possible fence points, sufficient to reduce the number of inputs to the logic tree to a value less than a predetermined limit, and inserts fence registers at those points. In this way, the number of inputs to the logic tree can be made small enough (e.g. 17 or less) to allow exhaustive testing of the circuit.

Claims

1. A method of automatically partitioning a logic tree to improve testability thereof, comprising the steps:

(a) identifying a set of driving bits for each of a set of points within the tree;

(b) for each of said set of points, identifying a set of splittable input bits that can be isolated by insertion of a self-test register at that point;

(c) identifying which of said points are possible fence points, having more than one splittable input bit; and

(d) selecting a sub-set of said possible fence points, sufficient to reduce the number of inputs to the logic tree to a value less than a predetermined limit, and inserting self-test registers at said sub-set of possible fence points.

2. A method according to claim 1 wherein the step of identifying the set of splittable bits at a point comprises:

(a) using a first method involving a local analysis of the driving bits and splittable bits in the vicinity of that point to derive the set of splittable bits for that point; and

(b) if the first method fails, using a second method involving an analysis of the driving bits in a cross-section of the whole tree.

3. A method according to claim 1 including a further step of optimizing said sub-set of possible fence points, by replacing in said sub-set two or more fence points in one level of the tree with a single fence point at a higher level of the tree.

4. A design automation method for digital electronic circuits, including the steps of synthesizing a circuit design including at least one logic tree, and then automatically partitioning said logic tree to improve testability thereof by means of an automatic partitioning method comprising the steps:

(a) identifying a set of driving bits for each of a set of points within the tree;

(b) for each of said set of points, identifying a set of splittable input bits that can be isolated by insertion of a self-test register at that point;

(c) identifying which of said points are possible fence points, having more than one splittable input bit; and

(d) selecting a sub-set of said possible fence points, sufficient to reduce the number of inputs to the logic tree to a value less than a predetermined limit, and inserting self-test registers at said sub-set of possible fence points.

5. A method according to claim 4 wherein the step of identifying the set of splittable bits at a point comprises:

(a) using a first method involving a local analysis of the driving bits and splittable bits in the vicinity of that point to derive the set of splittable bits for that point; and

(b) if the first method fails, using a second method involving an analysis of the driving bits in a cross-section of the whole tree.

6. A method according to claim 4 including a further step of optimizing said sub-set of possible fence points, by replacing in said sub-set two or more fence points in one level of the tree with a single fence point at a higher level of the tree.

7. A computer system, comprising:

(a) means for synthesizing a circuit design including at least one logic tree;

(b) means for identifying a set of driving bits for each of a set of points within the tree;

(c) means for identifying, for each of said set of points, a set of splittable input bits that can be isolated by insertion of a self-test register at that point;

(d) means for identifying which of said points are possible fence points, having more than one splittable input bit;

(e) means for selecting a sub-set of said possible fence points, sufficient to reduce the number of inputs to the logic tree to a value less than a predetermined limit; and

(f) means for inserting self-test registers at said sub-set of possible fence points to improve testability of said logic tree.