Method and system for automatic configuration of memory devices

• US 5,463,589 A
• Filed: 06/30/1994
• Issued: 10/31/1995
• Est. Priority Date: 06/30/1994
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Clark, C. W., Kraft, Douglas R., Gruender, Eugene H. Jr.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/269,427
• Time in Patent Office: 488 Days
• Field of Search: 365/230.01, 365/230.02, 365/189.01, 395/164, 395/165, 395/166, 395/425
• US Class Current: 365/230.01
• CPC Class Codes: G06F 12/0661 and decentralised selection

Abstract

A method and system for automatic configuration of memory devices having a same initial address. Initially, all of the memory devices in the computer system are disabled but one enabled memory device. An initial address of the enabled memory device is changed to a new unique address. Then, unless all of the memory devices have been enabled, one previously disabled memory device is enabled to produce a next enabled memory device having the initial address. The steps of changing the initial address of the enabled memory device to a new unique address and enabling a next enabled memory device having the initial address are then repeated until the initial address of each of the memory devices has been changed to a new unique address.

Claims

1. A method for automatic configuration of memory devices in a computer system upon startup or reset of the computer system, the computer system comprising a processor and the memory devices, each of the memory devices having a same initial address through which the processor accesses the memory devices at startup or reset of the computer system, the method performed by the computer system and comprising the steps of:

(a) disabling all of the memory devices but one enabled memory device;

(b) changing the initial address of the enabled memory device to a new unique address;

(c) enabling, unless all of the memory devices have been enabled, a next one of the memory devices to produce a next enabled memory device;

(d) repeating steps (b) and (c) until the initial address of each of the memory devices has been changed; and

(e) changing an address of one of the memory devices back to the initial address through which the processor accesses the one of the memory devices at startup or reset of the computer system.

2. The method of claim 1, wherein step (e) comprises changing an address of a largest memory device of the memory devices back to the initial address.

3. The method of claim 2, further comprising the steps of (f) changing an address of a next largest memory device of the memory devices to an address contiguous to a memory device having a last changed address;

and

(g) repeating step (f) until the address of each of the memory devices has been changed.

4. A method for automatic configuration of memory devices in a multiple board computer system upon startup or reset of the multiple board computer system, the multiple board computer system comprising a processor and the memory devices, each of the memory devices having a same initial address through which the processor accesses the memory devices at startup or reset of the computer system, the multiple board computer system having multiple boards comprising a motherboard including the processor and a memory system having one of the memory devices, and comprising one or more daughterboards connected to the motherboard by enable/disable lines in a daisy chain, each of the daughterboards including a different memory system having a different one of the memory devices, the method performed by the processor and comprising the steps of:

(a) disabling all of the enable/disable lines to disable all of the memory systems but one enabled memory system on the motherboard;

(b) changing the initial address of a memory device in the enabled memory system to a new unique address;

(c) enabling, unless all of the memory devices have been enabled, a next one of the enable/disable lines to one of the daughterboards to produce a next enabled memory system;

(d) repeating steps (b) and (c) until the initial address of each of the memory devices has been changed; and

(e) changing an address of one of the memory devices back to the initial address through which the processor accesses the one of the memory devices at startup or reset of the computer system.

5. The method of claim 4, wherein step (e) comprises changing an address of a largest memory device of the memory devices back to the initial address.

6. The method of claim 5, further comprising the steps of:

(f) changing an address of a next largest memory device of the memory devices to an address contiguous to a memory device having a last changed address; and

(g) repeating step (f) until the address of each of the memory devices has been changed.

7. A multiple board computer system comprising:

a motherboard having a processor and a memory system, the memory system having a memory device;

one or more daughterboards, each having a different memory system, the different memory system having a different memory device, each different memory device having an initial address through which the processor accesses the memory devices at startup or reset of the computer system, the daughterboards connected to the motherboard via enable/disable lines in a daisy chain; and

the processor disabling, upon startup or reset of the multiple board computer system, all of the enable/disable lines to disable all the memory systems but one enabled memory system on the motherboard, changing the initial address of the memory device in the enabled memory system to a new unique address, enabling a next one of the enable/disable lines to one of the daughterboards to produce a next enabled memory system, continuing to change the initial address to a different new unique address and enable a different next memory system until the initial address of each memory device has been changed, and changing an address of one of the memory devices back to the initial address through which the processor accesses the one of the memory devices at startup or reset of the computer system.

8. The multiple board computer system of claim 7 wherein at least one memory device is a RAM.

9. The multiple board computer system of claim 7 wherein at least one memory device is a DRAM.