Redundant memory channel array configuration with data striping and error correction capabilities

• US 5,463,643 A
• Filed: 03/07/1994
• Issued: 10/31/1995
• Est. Priority Date: 03/07/1994
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Gaskins, Darius D., Parks, Terry J.
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US08/207,009
• Time in Patent Office: 603 Days
• Field of Search: 371/40.1, 371/7, 371/10.1, 371/10.2, 371/11.1, 371/40.1, 371/40.2, 371/40.4, 395/425, 395/575
• US Class Current: 714/766
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.

Claims

1. A memory channel array system providing error correction capabilities, comprising:

a main memory;

a memory channel array controller; and

a first plurality of channels coupled between said memory channel array controller and said memory for transferring data between said memory channel array controller and said memory, said first plurality of channels including at least one redundant channel;

wherein said memory channel array controller includes;

a first plurality of channel controllers corresponding to said first plurality of channels, each of said first plurality of channel controllers being coupled to a corresponding one of said first plurality of channels, wherein each of said first plurality of channel controllers generates a signal indicative of incorrect data transferred on said corresponding channel; and

error correction logic coupled to said first plurality of channel controllers which receives data from each of said channel controllers and said incorrect data indicating signals from said channel controllers and outputs corrected data if one of said incorrect data indicating signals indicates incorrect data.

2. The memory channel array system of claim 1, wherein said memory channel array controller includes:

a buffer for connecting to one or more host devices, wherein said buffer is adapted for transferring and receiving data to and from said one or more host devices; and

a second plurality of internal buses coupled between said buffer and a second number of said first plurality of channel controllers, wherein said second plurality of internal buses transfers data between said buffer and said second number of said first plurality of channel controllers;

wherein said buffer stripes data across said second plurality of internal buses to said second number of said first plurality of channel controllers.

3. The memory channel array system of claim 2, wherein said at least one redundant channel comprises a parity channel for transferring parity data, said error correction logic comprises:

means for determining if one of said second number of said first plurality of channel controllers has received incorrect data; and

means for generating corrected data in place of said incorrect data which includes a multiplexor which selects between data output from a respective channel controller and corrected data;

the memory channel array controller further comprising;

parity generation logic coupled to said second plurality of internal buses for generating parity data based on data being transferred on said second plurality of internal buses to said second number of said first plurality of channel controllers; and

a parity bus coupled between said parity generation logic and the channel controller corresponding to said parity channel for transferring said parity data from said parity generation logic to said channel controller corresponding to said parity channel.

4. The memory channel array system of claim 1, wherein each of said first plurality of channels carries a plurality of data bits and at least one parity bit;

wherein each of said channel controllers includes parity error detection logic which analyzes said at least one parity bit and said corresponding channel and determines if a parity error has occurred, wherein said incorrect data indicating signals comprise parity error signals.

5. The memory channel array system of claim 1, wherein said memory channel array system is a RAMBUS memory system and said first plurality of channels conform to the RAMBUS specification.

6. A memory channel array system providing error correction capabilities, comprising:

a main memory;

a memory channel array controller;

a first plurality of channels coupled between said memory channel array controller and said main memory for transferring data between said memory channel array controller and said main memory, said first plurality of channels including at least one redundant channel;

wherein said memory channel array controller includes;

means for generating a first plurality of signals indicative of incorrect data transferred on said first plurality of channels;

error correction logic coupled to said first plurality of channels and said signal generating means which receives data from each of said channels and said incorrect data indicating signals from said signal generating means and outputs corrected data if one of said incorrect data indicating signals indicates incorrect data.

7. A memory channel array system providing data striping capabilities, comprising:

a main memory;

a memory channel array controller including a first plurality of channel controllers;

a first plurality of channels coupled between said memory channel array controller and said main memory for transferring data between said memory channel array controller and said main memory, said first plurality of channels including at least one redundant channel;

wherein said memory channel array controller includes;

a buffer for connecting to one or more host devices, wherein said buffer is adapted for transferring and receiving data to and from said one or more host devices;

a first plurality of internal buses coupled between said buffer and a first number of said first plurality of channel controllers, wherein said first plurality of internal buses transfer data between said first number of said first plurality of channel controllers and said buffer;

a second plurality of internal buses coupled between said buffer and a second number of said first plurality of channel controllers, wherein said second plurality of internal buses transfers data between said buffer and said second number of said first plurality of channel controllers;

wherein said buffer stripes data received from said one or more host devices across said second plurality of internal buses to said second number of said fist plurality of channel controllers.

8. The memory channel array system of claim 7, wherein said at least one redundant channel comprises a parity channel for transferring parity data, the memory channel array controller further comprising:

parity generation logic coupled to said second plurality of internal buses for generating parity data based on data being transferred on said second plurality of internal buses to said second number of said first plurality of channel controllers; and

a parity bus coupled between said parity generation logic and the channel controller corresponding to said parity channel for transferring said parity data from said parity generation logic to said channel controller corresponding to said parity channel.

9. The memory channel array system of claim 8, wherein said first number of said first plurality of channel controllers each generate a signal indicative of incorrect data transferred on said corresponding channel, the memory channel array controller further comprising:

error correction logic coupled to said first plurality of channel controllers which receives data from each of said channel controllers and said incorrect data indicating signals from said channel controllers and outputs corrected data on said first plurality of said internal buses if one of said incorrect data indicating signals indicates incorrect data.

10. A method of transferring data to and from main memory in a memory channel array system comprising a main memory, a memory channel array controller including a first plurality of channel controllers, and a first plurality of channels coupled between said memory channel array controller and said main memory for transferring data between said memory channel array controller and said main memory, wherein said first plurality of channels includes at least one redundant channel, and wherein the memory channel array controller includes redundant data generation logic, a buffer and a second plurality of internal buses coupled between the buffer and a second number of said first plurality of channel controllers, the method comprising the steps of:

the buffer receiving data from a host;

the buffer striping said data on the second plurality of internal buses to said second number of said first plurality of channel controllers;

the redundant data generation logic generating redundant data based on said received data from said host;

the redundant data generation logic providing said redundant data to said at least one redundant channel; and

the first plurality of channel controllers transferring said data received from said host and said redundant data to said main memory using said first plurality of channels.

11. The method of claim 10, wherein the memory channel array system further comprises error correction logic coupled between said first plurality of channel controllers and said buffer, the method further comprising:

the main memory transferring data to said first plurality of channel controllers;

the first plurality of channel controllers determining if a data error has occurred;

the error correction logic correcting the data subject to the data error using the redundant data; and

the memory channel array system outputting said data including said corrected data to a requesting host.