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Redundant memory channel array configuration with data striping and error correction capabilities

  • US 5,463,643 A
  • Filed: 03/07/1994
  • Issued: 10/31/1995
  • Est. Priority Date: 03/07/1994
  • Status: Expired due to Term
First Claim
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1. A memory channel array system providing error correction capabilities, comprising:

  • a main memory;

    a memory channel array controller; and

    a first plurality of channels coupled between said memory channel array controller and said memory for transferring data between said memory channel array controller and said memory, said first plurality of channels including at least one redundant channel;

    wherein said memory channel array controller includes;

    a first plurality of channel controllers corresponding to said first plurality of channels, each of said first plurality of channel controllers being coupled to a corresponding one of said first plurality of channels, wherein each of said first plurality of channel controllers generates a signal indicative of incorrect data transferred on said corresponding channel; and

    error correction logic coupled to said first plurality of channel controllers which receives data from each of said channel controllers and said incorrect data indicating signals from said channel controllers and outputs corrected data if one of said incorrect data indicating signals indicates incorrect data.

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