Method and apparatus for timing acquisition of partial response class IV signaling
First Claim
Patent Images
1. A phase detector comprising:
- quantizing means coupled to an input signal, said quantizing means outputting a quantized signal X;
logic means coupled to said quantizing means and receiving said quantized signal, said logic means providing as output a prediction signal, said logic means receiving as input first and second previous prediction signals Xn and Xn-1, said prediction signal having a value dependent on said first and second previous prediction signals and said quantized signal X.
2 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions Xn and Xn-1. The logic uses these values to determine the next value Xn+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.
18 Citations
23 Claims
-
1. A phase detector comprising:
-
quantizing means coupled to an input signal, said quantizing means outputting a quantized signal X; logic means coupled to said quantizing means and receiving said quantized signal, said logic means providing as output a prediction signal, said logic means receiving as input first and second previous prediction signals Xn and Xn-1, said prediction signal having a value dependent on said first and second previous prediction signals and said quantized signal X. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A phase detector comprising:
-
quantizing means coupled to an input signal, said quantizing means outputting a quantized signal X, said quantizing means comprising a first comparator coupled to a first reference value and to said input signal and a second comparator coupled to a second reference value and to said input signal; logic means coupled to said quantizing means and receiving said quantized signal, said logic means providing as output a prediction signal, said logic means receiving as input first and second previous prediction signals Xn and Xn-1, said logic means comprising a first OR gate coupled to an output of said first comparator and to an output of a first AND gate, a second AND gate coupled to an output of said first OR gate and to an inverted output of said second comparator, a second OR gate coupled to said output of said first comparator and to an output of said second comparator, a third OR gate coupled to an output of a third AND gate and to an output of said second OR gate; said prediction signal having a value dependent on said first and second previous prediction signals and said quantized signal X. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
-
Specification