Element placement method and apparatus
First Claim
1. An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, said method comprising the steps of:
- a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number; and
an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data and said overlapping data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data.
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Accused Products
Abstract
An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, the method including a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number, and an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data.
35 Citations
33 Claims
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1. An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, said method comprising the steps of:
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a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number; and an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data and said overlapping data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, comprising:
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a division step of dividing the circuit diagram into a plurality of partial circuits, each constituted by a plurality of branches; and a parallel processing step of simultaneously applying genetic algorithms to element placement of the respective partial circuits, wherein said parallel processing step includes a step of obtaining fitness used for the genetic algorithms with respect to the respective partial circuits with reference to information about a connection relationship between elements of each partial circuit as a placement target, and information about a placement result based on a best solution every predetermined number of generations of the immediately left partial circuit as a placement target. - View Dependent Claims (16)
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17. An LSI element placement apparatus for placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, said apparatus comprising:
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partial circuit data extraction means for sequentially extracting data of a predetermined number of branches included in the circuit diagram from a first terminal side of the circuit diagram so as to overlap the data by a predetermined number; and element placement means for performing an element placement operation based on a genetic algorithm in the partial circuit data extracted by said partial circuit data extraction means and said overlapping data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. An LSI element placement apparatus for placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, comprising:
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means for dividing the circuit diagram into a plurality of partial circuits, each constituted by a plurality of branches; and processing means for simultaneously applying genetic algorithms to element placement of the respective partial circuits, wherein said processing means includes means for obtaining fitness used for the genetic algorithms with respect to the respective partial circuits with reference to information about a connection relationship between elements of each partial circuit as a placement target, and information about a placement result based on a best solution every predetermined number of generations of the immediately left partial circuit as a placement target. - View Dependent Claims (33)
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Specification