Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory
First Claim
1. A sense circuit for tracking charge transfer through cell access transistors in a dynamic random access memory comprising:
- a pull-up node;
a capacitor which couples said pull-up node to a ground bus, said capacitor simulating digit line capacitance;
a first N-channel insulated-gate field-effect transistor (IGFET) which emulates cell access transistors and couples said pull-up node to a power supply bus, said first N-channel IGFET having a gate coupled to a dummy wordline driver through a dummy wordline; and
a CMOS inverter, said inverter havinga first P-channel IGFET which functions as a pull-up transistor,a second N-channel IGFET which functions as a pull-down transistor,an intermediate output coupled to both the power supply bus through the first P-channel IGFET and to the ground bus through the second N-channel IGFET, anda pair of inputs corresponding to the gates of said first P-channel IGFET and said second N-channel IGFET,both inputs being coupled to said pull-up node.
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Accused Products
Abstract
A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs a model access transistor to charge a pull-up node that is coupled to ground through a capacitor which simulates digit line capacitance. The pull-up node is coupled to the gate of a N-channel field-effect output transistor. When voltage on the node reaches the threshold voltage of the output transistor, the output transistor begins to turn on. The output from the output transistor (in this case, ground potential) is fed back to the gate of a P-channel device which couples the node to VCC. The P-channel device is used to pull up the node to VCC rapidly once the trip point (i.e., the threshold voltage) of the N-channel output transistor is reached. The sense circuit is reset for the next read cycle by sending a high signal to the gate of an N-channel reset transistor, which couples the capacitive node to ground.
16 Citations
13 Claims
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1. A sense circuit for tracking charge transfer through cell access transistors in a dynamic random access memory comprising:
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a pull-up node; a capacitor which couples said pull-up node to a ground bus, said capacitor simulating digit line capacitance; a first N-channel insulated-gate field-effect transistor (IGFET) which emulates cell access transistors and couples said pull-up node to a power supply bus, said first N-channel IGFET having a gate coupled to a dummy wordline driver through a dummy wordline; and a CMOS inverter, said inverter having a first P-channel IGFET which functions as a pull-up transistor, a second N-channel IGFET which functions as a pull-down transistor, an intermediate output coupled to both the power supply bus through the first P-channel IGFET and to the ground bus through the second N-channel IGFET, and a pair of inputs corresponding to the gates of said first P-channel IGFET and said second N-channel IGFET, both inputs being coupled to said pull-up node. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A sense circuit for tracking charge transfer through cell access transistors in a dynamic random access memory array comprising:
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(a) a dummy wordline to which a signal is applied; (b) an insulated-gate field-effect transistor (IGFET) which simulates access transistors in the array with respect to threshold voltage, said IGFET having a gate controlled by the signal on the dummy wordline; (c) a pull-up node that is charged from a power supply bus through the IGFET; (d) an output signal representative of the charge status on the pull-up node, said output signal being employed to trigger data latching in the memory. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification